C23C16/0218

METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM

There is provided a technique that includes: (a) loading a substrate into a process container at a loading temperature; (b) setting an interior of the process container to a film formation temperature; (c) forming a metal film on a surface of the substrate by supplying a process gas into the process container; (d) setting the interior of the process container to an unloading temperature lower than the loading temperature; and (e) unloading the substrate from the process container.

FILM-FORMING METHOD AND FILM-FORMING APPARATUS
20190371572 · 2019-12-05 ·

A film-forming method includes: loading a substrate by raising a plurality of lift pins of a mounting table provided in a processing container to receive the substrate and lowering the plurality of lift pins to mount the substrate on an upper surface of the mounting table, the plurality of lift pins being configured to protrude from the upper surface of the mounting table and to support the substrate; preheating the substrate by heating the substrate mounted on the mounting table in a state where an inert gas has been introduced into the processing container; and forming a film on the substrate by introducing a processing gas into the processing container.

Diamond electrode and method of manufacturing the same
10487396 · 2019-11-26 · ·

Disclosed are a method of manufacturing a diamond electrode by a chemical vapor deposition (CVD) process, and a diamond electrode manufactured by the method. The method of manufacturing the diamond electrode includes: introducing a carbon source gas to form niobium carbide (NbC) on a niobium substrate, immediately before depositing an electrically conductive diamond layer on the substrate by a hot-filament chemical vapor deposition (HFCVD) process; and depositing electrically conductive diamond layers on the substrate by two or more separate processes. Accordingly, a pinhole present during deposition of the electrically conductive diamond layer is filled such that the contact between an electrolyte and the substrate in an electrolytic environment will be minimized so as to retard the corrosion of the substrate, thereby providing a diamond electrode having a long life span.

Methods for semiconductor passivation by nitridation after oxide removal

In some embodiments, a semiconductor surface may be effectively passivated by nitridation, preferably using hydrazine, a hydrazine derivative, or a combination thereof. The surface may be the semiconductor surface of a transistor channel region. In some embodiments, native oxide is removed from the semiconductor surface and the surface is subsequently nitrided. In some other embodiments, a semiconductor surface oxide layer is formed at the semiconductor surface and the passivation is accomplished by forming a semiconductor oxynitride layer at the surface, with the nitridation contributing nitrogen to the surface oxide to form the oxynitride layer. The semiconductor oxide layer may be deposited by atomic layer deposition (ALD) and the nitridation may also be conducted as part of the ALD.

Electrical de-icing for aircraft

A heating element for in-flight de-icing of aircraft is disclosed. The heating element includes a carbon fiber material that is designed to be arranged on a component of an aircraft. The carbon fiber material includes at least two electrical contacts for connecting to an electrical wiring system, and at least one insulation layer for electrical insulation.

HEXAGONAL BORON NITRIDE THIN FILM AND METHOD FOR PRODUCING THE SAME

The present invention is to provide: a method for producing a novel hexagonal boron nitride thin film suitable for industrial use such as application to electronics, in which a hexagonal boron nitride thin film having a large area, a uniform thickness of 1 nm or more, with few grain boundaries can be produced inexpensively; and a hexagonal boron nitride thin film. The hexagonal boron nitride thin film according to the present invention is characterized by having a thickness of 1 nm or more, and an average value of the full width at half maximum of the E.sub.2g peak obtained from Raman spectrum of 9 to 20 cm.sup.1.

METHODS AND APPARATUS FOR HIGH REFLECTIVITY ALUMINUM LAYERS

Methods and apparatus for increasing reflectivity of an aluminum layer on a substrate. In some embodiments, a method of depositing an aluminum layer on a substrate comprises depositing a layer of cobalt or cobalt alloy or a layer of titanium or titanium alloy on the substrate with a chemical vapor deposition (CVD) process, pre-treating the layer of cobalt or cobalt alloy with a thermal hydrogen anneal at a temperature of approximately 400 degrees Celsius if a top surface of the layer of cobalt or cobalt alloy is compromised, and depositing a layer of aluminum on the layer of cobalt or cobalt alloy or the layer of titanium or titanium alloy with a CVD process at a temperature of approximately 120 degrees Celsius. Pre-treatment of the layer of cobalt or cobalt alloy may be accomplished for a duration of approximately 60 seconds to approximately 120 seconds.

Superlubricity coating containing carbon nanotubes

A method for producing a structure containing an array of MWCNTs on a metal substrate, comprising: (i) subjecting a metal substrate to a surface oxidation process at a first elevated temperature in an oxygen-containing atmosphere and under a first reduced pressure; (ii) subjecting the metal substrate to a surface reduction process at a second elevated temperature in a reducing atmosphere and under a second reduced pressure of at least 0.01 atm and less than 1 atm to result in reduction of the surface of said metal substrate, wherein the reducing atmosphere contains hydrogen gas; (iii) subjecting the metal substrate to a third reduced pressure of no more than 0.1 atm; and (iv) contacting the metal substrate, while at the third reduced pressure and under an inert or reducing atmosphere, with an organic substance at a third elevated temperature for suitable time to produce the MWCNTs on the metal substrate.

Selective cobalt deposition on copper surfaces

Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.

Epitaxial growth methods and structures thereof

A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.