A silicon carbide wafer and a method of fabricating the same are provided. In the silicon carbide wafer, a ratio (V:N) of a vanadium concentration to a nitrogen concentration is in a range of 2:1 to 10:1, and a portion of the silicon carbide wafer having a resistivity greater than 10.sup.12 Ω.Math.cm accounts for more than 85% of an entire wafer area of the silicon carbide wafer.

This disclosure relates to a superlattice structure, an LED epitaxial structure, a display device, and a method for manufacturing the LED epitaxial structure. The superlattice structure includes at least two superlattice units which are grown in stacking layers. Each of the at least two superlattice units includes a first n-type GaN layer, a second n-type GaN layer, a first n-type GaInN layer, and a second n-type GaInN layer which are grown in stacking layers. The first n-type GaN layer has a doping concentration which is constant along a growth direction, the second n-type GaN layer has a doping concentration which gradually increases along the growth direction, the first n-type GaInN layer has a doping concentration which gradually decreases along the growth direction, and the second n-type GaInN layer has a doping concentration which is constant along the growth direction.

In the present invention, a chemical-vapor-deposition silicon carbide (SIC) bulk having an improved etching characteristic includes silicon carbide (SIC) manufactured by a chemical vapor deposition method using MTS (methyltrichlorosilane), hydrogen (H.sub.2), and nitrogen (N.sub.2) gases. The SIC manufactured by the chemical vapor deposition method is β-SiC (3C-SiC), and 6H-SiC is present in the SIC manufactured by the chemical vapor deposition method. Five peaks having a reference code of 03-065-0360 and a peak having a reference code of 00-049-1428 are confirmed to be present from XRD analysis of the silicon carbide bulk, and a nitrogen concentration value is 4.0×10.sup.18 atoms/cm.sup.3 or more at a depth of 1,500 nm or more from the surface of the bulk, which is a metastable layer.

A method of forming a silicon germanium layer on a surface of a substrate and a system for forming a silicon germanium layer are disclosed. Examples of the disclosure provide a method that includes providing a plurality of growth precursors to control and/or promote parasitic gas-phase and surface reactions, such that greater control of the film (e.g., thickness and/or composition) uniformity can be realized.

The present invention provides a method for producing a Group III nitride semiconductor device which can relax strain between a Group III nitride semiconductor layer containing In and a semiconductor layer adjacent thereto, and a production method therefor. The well layer is a Group III nitride semiconductor layer containing In. The barrier layer is a Group III nitride semiconductor layer. The well layer and the barrier layer are brought into contact with each other in at least one of growing a well layer and growing a barrier layer. A gas containing hydrogen gas as a carrier gas is used in growing a well layer and growing a barrier layer. In growing a barrier layer, the flow rate of hydrogen gas is higher than the flow rate of hydrogen gas in growing a well layer.

A surface-coated cutting tool includes a base material and a coating formed on a surface of the base material. The coating includes a first hard coating layer including crystal grains having a sodium chloride-type crystal structure. The crystal grain has a layered structure in which a first layer composed of nitride or carbonitride of Al.sub.xTi.sub.1-x and a second layer composed of nitride or carbonitride of Al.sub.yTi.sub.1-y are stacked alternately into one or more layers. The first layer each has an atomic ratio x of Al varying in a range of 0.6 or more to less than 1. The second layer each has an atomic ratio y of Al varying in a range of 0.45 or more to less than 0.6. The largest value of difference between the atomic ratio x and the atomic ratio y is 0.05≤x−y≤0.5.

Variations in device characteristics in a plane parallel to the principal surface of a semiconductor wafer are suppressed. A semiconductor epitaxial wafer includes a semiconductor wafer and a first conductivity type semiconductor epitaxial layer that is disposed on a principal surface of the semiconductor wafer and contains a first conductivity type impurity, and the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurity in the semiconductor epitaxial layer have a positive correlation in a plane parallel to the principal surface of the semiconductor wafer.

Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.

A chemical vessel is disclosed comprising a dip tube and a level sensor tube arranged in an elongated counterbore incorporated into a housing of the chemical vessel. The chemical vessel may be configured to allow a pushback routine to take place, whereby a level of liquid in the chemical vessel is reduced to a point that the dip tube is free from liquid inside the dip tube or at the bottom of the dip tube. Once the dip tube is free of the liquid, then a vacuum source may be used to purge vapor within the chemical vessel without the risk of damage to the vacuum source.

The present application provides a reaction device for improving epitaxial growth uniformity, provided with a main inject port on one side and an exhaust port on the other side, wherein a base is provided between the main inject port and the exhaust port; the reaction cavity is provided with first and second inject pipes; the length directions of the first and second inject pipes are perpendicular to a connecting line between the main inject port and the exhaust port; the lengths of the first and second inject pipes are both equal to the radius of the base; the first and second inject pipes are located in a straight line along the length directions; the first and second inject pipes are each provided with a plurality of holes; and the plurality of holes on the first and second inject pipes are located above the wafer placed on the base.