A method of fabricating a semiconductor device includes providing a substrate, implementing a growth procedure to form a semiconductor layer supported by the substrate, performing an anneal of the semiconductor layer, the anneal being conducted at a higher temperature than the growth procedure, and repeating the growth procedure and the anneal. The anneal is conducted at or above a decomposition temperature for the semiconductor layer.

Filled carbon nanotubes (CNTs) and methods of synthesizing the same are provided. An in situ chemical vapor deposition technique can be used to synthesize CNTs filled with metal sulfide nanowires. The CNTs can be completely and continuously filled with the metal sulfide fillers up to several micrometers in length. The filled CNTs can be easily collected from the substrates used for synthesis using a simple ultrasonication method.

Methods and equipment for the removal of semiconductor wafers grown on the top surface of a single crystal silicon substrate covered by a porous silicon separation layer by using IR irradiation of the porous silicon separation layer to initiate release of the semiconductor wafer from the substrate, particularly at edges (and corners) of the top surface of the substrate.

A reactor system may comprise a first reaction chamber and a second reaction chamber. The first and second reaction chambers may each comprise a reaction space enclosed therein, a susceptor disposed within the reaction space, and a fluid distribution system in fluid communication with the reaction space. The susceptor in each reaction chamber may be configured to support a substrate. The reactor system may further comprise a first reactant source, wherein the first reaction chamber and the second reaction chamber are fluidly coupled to the first reactant source at least partially by a first reactant shared line. The reactor system may be configured to deliver a first reactant from the first reactant source to the first reaction chamber and a second reaction chamber through the first reactant shared line.

An epitaxial silicon carbide single crystal wafer having a small depth of shallow pits and having a high quality silicon carbide single crystal thin film and a method for producing the same are provided. The epitaxial silicon carbide single crystal wafer according to the present invention is produced by forming a buffer layer made of a silicon carbide epitaxial film having a thickness of 1 μm or more and 10 μm or less by adjusting the ratio of the number of carbon to that of silicon (C/Si ratio) contained in a silicon-based and carbon-based material gas to 0.5 or more and 1.0 or less, and then by forming a drift layer made of a silicon carbide epitaxial film at a growth rate of 15 μm or more and 100 μm or less per hour. According to the present invention, the depth of the shallow pits observed on the surface of the drift layer can be set at 30 nm or less.

A method for manufacturing monocrystalline graphene, includes supplying an aromatic carbon gas onto a single-crystalline metal catalyst to manufacture the monocrystalline graphene.

In some embodiments, the present disclosure pertains to methods of forming single-crystal graphenes by: (1) cleaning a surface of a catalyst; (2) annealing the surface of the catalyst; (3) applying a carbon source to the surface of the catalyst; and (4) growing single-crystal graphene on the surface of the catalyst from the carbon source. Further embodiments of the present disclosure also include a step of separating the formed single-crystal graphene from the surface of the catalyst. In some embodiments, the methods of the present disclosure also include a step of transferring the formed single-crystal graphene to a substrate. Additional embodiments of the present disclosure also include a step of growing stacks of single crystals of graphene.

Provided is a method of manufacturing an epitaxial wafer, which includes vapor-phase growing an epitaxial layer on a substrate W placed on a susceptor 3 in a state where an upper surface 4b1 of a lift pin 4 inserted in a through-hole H of the susceptor 3 retracts or projects with respect to an upper opening H1a of the through-hole H. A level difference D from the upper surface 4b1 of the lift pin 4 to the opening H1a of the through-hole H is measured with laser light, and outputs, during epitaxial growth, of heaters 9 located above and beneath the susceptor 3 are adjusted on the basis of the measured level difference D. Thus, a method of manufacturing an epitaxial wafer, which facilitates adjustment of the outputs of the heat sources during epitaxial growth, is provided.

The present disclosure relates to a method that includes depositing a first layer onto a substrate, depositing a second layer onto a surface of the first layer, and separating the substrate from the second layer, where the substrate includes a first III-V alloy, the second layer includes second III-V alloy, and the first layer includes a material that includes at least two of a Group 1A element, a Group 2A element, a Group 6A element, and/or a halogen.

There is provided a method of manufacturing a group III nitride semiconductor substrate including: a fixing step S10 of fixing abase substrate, which includes a group III nitride semiconductor layer having a semipolar plane as a main surface, to a susceptor; a first growth step S11 of forming a first growth layer by growing a group III nitride semiconductor over the main surface of the group III nitride semiconductor layer in a state in which the base substrate is fixed to the susceptor using an HVPE method; a cooling step S12 of cooling a laminate including the susceptor, the base substrate, and the first growth layer; and a second growth step S13 of forming a second growth layer by growing a group III nitride semiconductor over the first growth layer in a state in which the base substrate is fixed to the susceptor using the HVPE method.