Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a WARP value of 3.5 μm or less, as measured with the back surface of the indium phosphide substrate facing upward.

Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a BOW value of −2.0 to 2.0 μm, as measured with the back surface of the indium phosphide substrate facing upward.

A method for manufacturing a cubic silicon carbide film includes: a first step of introducing a carbon-containing gas onto a silicon substrate and rapidly heating the silicon substrate to an epitaxial growth temperature of cubic silicon carbide so as to carbonize a surface of the silicon substrate and form a cubic silicon carbide film; and a second step of introducing a carbon-containing gas and a silicon-containing gas onto the cubic silicon carbide film while maintaining the cubic silicon carbide film at the epitaxial growth temperature of cubic silicon carbide, so as to allow further epitaxial growth of the cubic silicon carbide film.

A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

In order to reduce edge defects efficiently and sufficiently, a method for manufacturing a SiC epitaxial wafer according to the present invention is a method for manufacturing a SiC epitaxial wafer that forms a SiC epitaxial layer on top of a SiC single crystal substrate having an off angle, and includes a rough polishing step for subjecting an outer circumferential edge on a starting side of step-flow growth in the SiC single crystal substrate to rough polishing before forming the SiC epitaxial layer; and a final polishing step for further polishing for finish.

An alumina substrate having a carbon-containing phase with an AlN layer formed on a surface of the alumina substrate.

A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

Thin freestanding nitride veneers can be used for the fabrication of semiconductor devices. These veneers are typically less than 100 microns thick. The use of thin veneers also eliminates the need for subsequent wafer thinning for improved thermal performance and 3D packaging.

Methods of forming a crystalline strontium titanate layer may include providing a substrate with a crystal enhancement surface (e.g., Pt), depositing strontium titanate by atomic layer deposition, and conducting a post-deposition anneal to crystallize the strontium titanate. Large single crystal domains may be formed, laterally extending greater distances than the thickness of the strontium titanate and demonstrating greater ordering than the underlying crystal enhancement surface provided to initiate ALD. Functional oxides, particularly perovskite complex oxides, can be heteroepitaxially deposited over the crystallized STO.

A method for manufacturing a large-scale single crystal monolayer of hBN including: preparing a single crystal copper substrate of (111) face in a chemical vapor deposition (CVD) apparatus; removing impurities of the single crystal copper substrate of (111) face; forming a plurality of hBN crystal seeds by depositing a vaporized ammonia borane or a vaporized borazine on the surface of the single crystal copper substrate from which the impurities are removed; and forming a large-scale single crystal monolayer of hBN grown by mutual coherence between the hBN crystal seeds, an apparatus for manufacturing the same, and a substrate for a monolayer UV graphene growth using the same.