C30B25/20

GAN CRYSTAL AND GAN SUBSTRATE

Provided are: a GaN crystal used in a substrate for a nitride semiconductor device having a horizontal device structure, such as a GaN-HEMT; and a GaN substrate used for the production of a nitride semiconductor device having a horizontal device structure, such as a GaN-HEMT. The GaN crystal and the GaN substrate each include a surface having an inclination of 10° or less from a (0001) crystal plane and an area of 5 cm.sup.2 or more, and have an Mn concentration of 1.0 × 10.sup.16 atoms/cm.sup.3 or higher but lower than 1.0 × 10.sup.19 atoms/cm.sup.3 and a total donor impurity concentration of lower than 5.0 × 10.sup.16 atoms/cm.sup.3.

GAN CRYSTAL AND GAN SUBSTRATE

Provided are: a GaN crystal used in a substrate for a nitride semiconductor device having a horizontal device structure, such as a GaN-HEMT; and a GaN substrate used for the production of a nitride semiconductor device having a horizontal device structure, such as a GaN-HEMT. The GaN crystal and the GaN substrate each include a surface having an inclination of 10° or less from a (0001) crystal plane and an area of 5 cm.sup.2 or more, and have an Mn concentration of 1.0 × 10.sup.16 atoms/cm.sup.3 or higher but lower than 1.0 × 10.sup.19 atoms/cm.sup.3 and a total donor impurity concentration of lower than 5.0 × 10.sup.16 atoms/cm.sup.3.

VAPOR DEPOSITION DEVICE AND METHOD OF PRODUCING EPITAXIAL WAFER
20230203705 · 2023-06-29 ·

A vapor phase growth system includes a process chamber that includes a susceptor lifting mechanism that raises and lowers the susceptor between a first position and a second position. With the susceptor in the first position, the top surface of the susceptor is above the bottom surface of the preheating ring, and a source gas distribution space with a predetermined height dimension is secured between the top surface of the susceptor and the bottom surface of a ceiling plate of the reaction vessel body. With the susceptor in the second position, the top surface of the susceptor is located below the bottom surface of a preheating ring, and a substrate loading/unloading space, which has a greater height dimension than that of the source gas distribution space, is secured between the top surface of the susceptor and the bottom surface of the preheating ring.

VAPOR DEPOSITION DEVICE AND METHOD OF PRODUCING EPITAXIAL WAFER
20230203705 · 2023-06-29 ·

A vapor phase growth system includes a process chamber that includes a susceptor lifting mechanism that raises and lowers the susceptor between a first position and a second position. With the susceptor in the first position, the top surface of the susceptor is above the bottom surface of the preheating ring, and a source gas distribution space with a predetermined height dimension is secured between the top surface of the susceptor and the bottom surface of a ceiling plate of the reaction vessel body. With the susceptor in the second position, the top surface of the susceptor is located below the bottom surface of a preheating ring, and a substrate loading/unloading space, which has a greater height dimension than that of the source gas distribution space, is secured between the top surface of the susceptor and the bottom surface of the preheating ring.

SILICON CARBIDE WAFER AND METHOD FOR MANUFACTURING THE SAME

A silicon carbide wafer includes a base wafer that is made of silicon carbide and doped with an n-type impurity, and an epitaxial layer that is arranged on a main surface of the base wafer, made of silicon carbide and doped with an n-type impurity. The base wafer has a thickness t1 and an average impurity concentration n1, and the epitaxial layer has a thickness t2 and an average impurity concentration n2. The base wafer and the epitaxial layer are configured so as to satisfy a mathematical formula 1:


−0.0178<0.012+(t2/t1)×0.057-(n2/n1)×0.029-{(t2/t1)-0.273}×{(n2/n1)-0.685}×0.108<0.0178.  [Formula 1]

SILICON CARBIDE WAFER AND METHOD FOR MANUFACTURING THE SAME

A silicon carbide wafer includes a base wafer that is made of silicon carbide and doped with an n-type impurity, and an epitaxial layer that is arranged on a main surface of the base wafer, made of silicon carbide and doped with an n-type impurity. The base wafer has a thickness t1 and an average impurity concentration n1, and the epitaxial layer has a thickness t2 and an average impurity concentration n2. The base wafer and the epitaxial layer are configured so as to satisfy a mathematical formula 1:


−0.0178<0.012+(t2/t1)×0.057-(n2/n1)×0.029-{(t2/t1)-0.273}×{(n2/n1)-0.685}×0.108<0.0178.  [Formula 1]

GaN SUBSTRATE

A disk-shaped GaN substrate has a diameter of 2 inches or more has a front surface tilted with a tilt angle of 45° or more and 135° or less relative to the (0001) plane in a tilt direction within a range of ±5° around the <10-10> direction, and a back surface which is a main surface opposite to the front surface. The GaN substrate has a first point positioned in a direction perpendicular to the c-axis when viewed from the center thereof, on the side surface thereof. A single diffraction peak appears in an X-ray diffraction pattern obtained by θ scan in which an X-ray (CuKα.sub.1: wavelength: 0.1542 nm) is incident to the first point and the incident angle θ of the incident X-ray is varied while the 2θ angle of the diffracted X-ray is fixed to twice the Bragg angle of 28.99° of the {11-20} plane.

GaN SUBSTRATE

A disk-shaped GaN substrate has a diameter of 2 inches or more has a front surface tilted with a tilt angle of 45° or more and 135° or less relative to the (0001) plane in a tilt direction within a range of ±5° around the <10-10> direction, and a back surface which is a main surface opposite to the front surface. The GaN substrate has a first point positioned in a direction perpendicular to the c-axis when viewed from the center thereof, on the side surface thereof. A single diffraction peak appears in an X-ray diffraction pattern obtained by θ scan in which an X-ray (CuKα.sub.1: wavelength: 0.1542 nm) is incident to the first point and the incident angle θ of the incident X-ray is varied while the 2θ angle of the diffracted X-ray is fixed to twice the Bragg angle of 28.99° of the {11-20} plane.

INDIUM PHOSPHIDE SUBSTRATE, METHOD OF INSPECTING INDIUM PHOSPHIDE SUBSTRATE, AND METHOD OF PRODUCING INDIUM PHOSPHIDE SUBSTRATE

An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation σ1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less.

EPITAXIAL SILICON CARBIDE SINGLE CRYSTAL WAFER AND PROCESS FOR PRODUCING THE SAME

An epitaxial silicon carbide single crystal wafer having a small depth of shallow pits and having a high quality silicon carbide single crystal thin film and a method for producing the same are provided. The epitaxial silicon carbide single crystal wafer according to the present invention is produced by forming a buffer layer made of a silicon carbide epitaxial film having a thickness of 1 μm or more and 10 μm or less by adjusting the ratio of the number of carbon to that of silicon (C/Si ratio) contained in a silicon-based and carbon-based material gas to 0.5 or more and 1.0 or less, and then by forming a drift layer made of a silicon carbide epitaxial film at a growth rate of 15 μm or more and 100 μm or less per hour. According to the present invention, the depth of the shallow pits observed on the surface of the drift layer can be set at 30 nm or less.