Graphene oxide is used as an insulation barrier layer for metal deposition. After patterning and modification, the chemical characteristics of graphene oxide are induced. It can be used as the catalyst for electroless plating in the metallization process, so that the metal is only deposited on the patterned area. It provides the advantages of improving reliability and yield. The metallization structure includes a substrate, a graphene oxide catalytic layer, and a metal layer. It may be widely applied to the metallization of the fine pitch metal of a semiconductor package as well as the fine pitch wires of a printed circuit board (PCB), touch panels, displays, fine electrodes of solar cells, and so on.

A symbol button for a vehicle includes: a button body; a button surface portion positioned at an upper portion of the button body; a symbol printing portion positioned on the button surface portion; an anti-plating portion positioned at a lower portion of the button body; and a metal plating layer positioned at the outside of a button excluding the symbol printing portion and the anti-plating portion.

A method of making a work piece without the use of an auxiliary anode and a work piece created using the method are provided. The work piece includes a main face being generally planar. The work piece also includes a first area comprising a plateable resin configured to be plated using the plating process without the auxiliary anode and having a first current density during the plating process. Additionally, the work piece includes a second area comprising a non-plateable resin configured to not be plated using the plating process without the auxiliary anode. The first area and the second area are determined by a process referencing a predetermined minimum current density value with the first current density being greater than the predetermined minimum current density value.

Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.

A method for producing a galvanically decorated component with a symbol or structure of a transilluminatable design incorporated in the surface produces the component from an electroplatable plastic in an injection-molding process, and the symbol or structure is produced from a non-electroplatable, electroplating-resistant printed image. The printed image is transferred from a carrier onto the component using thermal transfer by being activated using a laser. A galvanically decorated component is produced by the method.

Methods of patterning electroless metals on a substrate are presented. The substrate is covered by a blocking reagent. After formation of a catalyst blocking layer on the substrate, portions of the catalyst blocking layer are removed to form a circuit pattern. A catalyst is placed the surfaces of both the catalyst blocking layer and the exposed substrate. The catalyst blocking layer prevents or reduces catalytic activity of the catalyst. Electroless metal plating is performed to plate a metal at the active portions of the catalyst.

The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

A self-cleaning transparent conductive surface includes a hydrophobic film and a metal nano-web coupled to the hydrophobic film. The metal nano-web imparts conductive properties to the surface of the film and texturing formed by either the hydrophobic film, substrate or metal nano-web create a super-hydrophobic surface. This super-hydrophobic and conductive surface may be created by etching and layering a metal nano-web over the surface of a hydrophobic film or a rigid substrate, the metal grid may the hydrophobic film or substrate may also be etched in a moth's eye pattern. Both the hydrophobic film or substrate and metal nano-web may be coated in a layer of hydrophobic material to further increase the hydrophobic effect.

A plating method includes a first mask forming step of ejecting a UV-curable ink in the form of ink droplets from an inkjet head so as to have the ejected ink droplets land on a plating target object and to form a first plating mask on the plating target object, a catalyst applying step of applying a catalyst for deposition of plating material to the plating target object on which the first plating mask is formed, a second mask forming step of having the ink droplets land on the first plating mask so as to form a second plating mask on the first plating mask, a plating step of performing electroless plating to the plating target object subsequent to the second mask forming step, and a mask removing step of removing the first plating mask and the second plating mask from the plating target object subsequent to the plating step.

A ceramic circuit substrate is suitable for silver nanoparticle bonding of semiconductor elements and has excellent close adhesiveness with a power module sealing resin. A ceramic circuit substrate has a copper plate bonded, by a braze material, to both main surfaces of a ceramic substrate including aluminum nitride or silicon nitride, the copper plate of at least one of the main surfaces being subjected to silver plating, wherein: the copper plate side surfaces are not subjected to silver plating; the thickness of the silver plating is 0.1 m to 1.5 m; and the arithmetic mean roughness Ra of the surface roughness of the circuit substrate after silver plating is 0.1 m to 1.5 m.