Patent classifications
C30B29/406
High quality group-III metal nitride seed crystal and method of making
High quality ammonothermal group III metal nitride crystals having a pattern of locally-approximately-linear arrays of threading dislocations, methods of manufacturing high quality ammonothermal group III metal nitride crystals, and methods of using such crystals are disclosed. The crystals are useful for seed bulk crystal growth and as substrates for light emitting diodes, laser diodes, transistors, photodetectors, solar cells, and for photoelectrochemical water splitting for hydrogen generation devices.
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR WAFER
A method for manufacturing a semiconductor device includes: preparing a processed wafer having a gallium nitride (GaN) wafer and an epitaxial layer on the GaN wafer; forming a device constituent part in a portion of the processes wafer adjacent to a front surface provided by the epitaxial layer; forming a modified layer inside of the processed wafer by applying a laser beam from a back surface side opposite to the front surface side: and dividing the processed wafer at the modified layer. The processed wafer prepared includes a reflective layer for reflecting the laser beam at a position separated from a planned formation position, where the modified layer is to be formed, by a predetermined distance toward the front surface side. The reflective layer contains a layer having a refractive index different from that of a GaN single crystal of an epitaxial layer.
METHOD OF MANUFACTURING AND GROUP III NITRIDE CRYSTAL
A method of manufacturing a group III nitride crystal includes: preparing a seed substrate; causing surface roughness on the surface of the seed substrate; and supplying a group III element oxide gas and a nitrogen element-containing gas to grow a group III nitride crystal on the seed substrate.
GROWTH OF A-B CRYSTALS WITHOUT CRYSTAL LATTICE CURVATURE
A III-V-, IV-IV- or II-VI-compound single crystal comprising III-, IV- or II-precipitates and/or unstoichiometrical III-V-, IV-VI-, or II-VI-inclusions, wherein concentration of the respective precipitates and/or inclusions is no more than 1×10.sup.4 cm.sup.−3
METHOD FOR PRODUCING A LAYER OF ALUMINIUM NITRIDE (ALN) ON A STRUCTURE OF SILICON OR III-V MATERIALS
A method for producing an aluminium nitride (AlN)-based layer on a structure with the basis of silicon (Si) or with the basis of a III-V material, may include several deposition cycles performed in a plasma reactor comprising a reaction chamber inside which is disposed a substrate having the structure. Each deposition cycle may include at least the following: deposition of aluminium-based species on an exposed surface of the structure, the deposition including at least one injection into the reaction chamber of an aluminium (Al)-based precursor; and nitridation of the exposed surface of the structure, the nitridation including at least one injection into the reaction chamber of a nitrogen (N)-based precursor and the formation in the reaction chamber of a nitrogen-based plasma. During the formation of the nitrogen-based plasma, a non-zero polarisation voltage V.sub.bias_.sub.substrate may be applied to the substrate.
Epitaxial structure of N-face group III nitride, active device, and method for fabricating the same with integration and polarity inversion
The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-Al.sub.yGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-Al.sub.yGaN layer to the junction between the i-GaN channel layer and the i-Al.sub.xGaN layer.
HEATER FOR RETROGRADE SOLVOTHERMAL CRYSTAL GROWTH, METHOD OF MAKING, AND METHOD OF USE
Embodiments of the disclosure an apparatus for solvothermal crystal growth, comprising: a pressure vessel having a cylindrical shape and a vertical orientation; a cylindrical heater having an upper zone and a lower zone that can be independently controlled; at least one end heater; and an inward-facing surface of a baffle placed within 100 millimeters of a bottom end or top end surface of the growth chamber. The end heater is configured to enable: a variation in the temperature distribution along a first surface to be less than about 10° C., and a variation in the temperature distribution along a second surface to be less than about 20° C., during a crystal growth process. The first surface has a cylindrical shape and is positioned within the pressure vessel, and the second surface comprises an inner diameter of the growth chamber, and the temperature distribution along the second surface is created within an axial distance of at least 100 millimeters of an end of the growth chamber proximate to the first surface.
Compound semiconductor substrate, a pellicle film, and a method for manufacturing a compound semiconductor substrate
A method for manufacturing a compound semiconductor substrate that can achieve thinning of SiC film, wherein the method includes forming a SiC film on one principal surface side of a Si substrate and forming a recessed part in which a bottom surface is Si in a central part of another principal surface of the Si substrate.
Method of forming a high quality group-III metal nitride boule or wafer using a patterned substrate
A method for forming a laterally-grown group III metal nitride crystal includes providing a substrate, the substrate including one of sapphire, silicon carbide, gallium arsenide, silicon, germanium, a silicon-germanium alloy, MgAl.sub.2O.sub.4 spinel, ZnO, ZrB.sub.2, BP, InP, AlON, ScAlMgO.sub.4, YFeZnO.sub.4, MgO, Fe.sub.2NiO.sub.4, LiGa.sub.5O.sub.8, Na.sub.2MoO.sub.4, Na.sub.2WO.sub.4, In.sub.2CdO.sub.4, lithium aluminate (LiAlO.sub.2), LiGaO.sub.2, Ca.sub.8La.sub.2(PO.sub.4).sub.6O.sub.2, gallium nitride, or aluminum nitride (AlN), forming a pattern on the substrate, the pattern comprising growth centers having a minimum dimension between 1 micrometer and 100 micrometers, and being characterized by at least one pitch dimension between 20 micrometers and 5 millimeters, growing a group III metal nitride from the pattern of growth centers vertically and laterally, and removing the laterally-grown group III metal nitride layer from the substrate. A laterally-grown group III metal nitride layer coalesces, leaving an air gap between the laterally-grown group III metal nitride layer and the substrate or a mask thereupon.
Optimized heteroepitaxial growth of semiconductors
A method of performing heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and a second precursor gas, to form a heteroepitaxial growth of one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN on the substrate; wherein the substrate comprises one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN; wherein the carrier gas is H.sub.2, wherein the first precursor is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the second precursor is one of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), H.sub.2Te (hydrogen telluride), SbH.sub.3 (hydrogen antimonide), H.sub.2S (hydrogen sulfide), and NH.sub.3 (ammonia). The process may be an HVPE (hydride vapor phase epitaxy) process.