A multilayer ceramic capacitor includes: a multilayer structure in which each of dielectric layers and each of internal electrode layers are stacked, wherein a relationship of 8.0≥I.sub.A/I.sub.B>1.40 is satisfied in a TSDC (Thermally Stimulated Depolarization Currents) of temperature elevation rate of 10 degrees C./min under a condition of 130 degrees C., 5 V/μm and a polarization of 30 min, when a peak current value on a lower temperature side in a temperature range of 130 degrees C. to 190 degrees C. is I.sub.A and a peak current value on a higher temperature side in a temperature range of 190 degrees C. to 280 degrees C. is I.sub.B.

Provided is a polycrystalline ceramic substrate to be bonded to a compound semiconductor substrate with a bonding layer interposed therebetween, wherein at least one of relational expression (1) 0.7<α.sub.1/α.sub.2<0.9 and relational expression (2) 0.7<α.sub.3/α.sub.4<0.9 holds, where α.sub.1 represents a linear expansion coefficient of the polycrystalline ceramic substrate at 30° C. to 300° C. and α.sub.2 represents a linear expansion coefficient of the compound semiconductor substrate at 30° C. to 300° C., and α.sub.3 represents a linear expansion coefficient of the polycrystalline ceramic substrate at 30° C. to 1000° C. and α.sub.4 represents a linear expansion coefficient of the compound semiconductor substrate at 30° C. to 1000° C.

A pillar shaped honeycomb structure for induction heating, the honeycomb structure being made of ceramics and including: an outer peripheral wall; and a partition wall disposed on an inner side of the outer peripheral wall, the partition wall defining a plurality of cells, each of the cells penetrating from one end face to other end face to form a flow path, wherein a composite material containing a conductor and a non-conductor is provided in the cells in a region of 50% or less of the total length of the honeycomb structure from one end face, and wherein the conductor is a conductor that generates heat in response to a change in a magnetic field.

A multi-layer ceramic capacitor includes: a first region including a polycrystal including, as a main component, crystal grains free from intragranular pores; a second region that includes a polycrystal including, as a main component, crystal grains including intragranular pores and includes a higher content of silicon than a content of silicon in the first region; a capacitance forming unit including ceramic layers laminated along a first direction, and internal electrodes disposed between the ceramic layers; and a protective portion including a cover that covers the capacitance forming unit and constitutes a main surface facing in the first direction, a side margin constituting a side surface facing in a second direction orthogonal to the first direction, and a ridge constituting a connection portion, the connection portion connecting the main surface and the side surface to each other. The ceramic layers include the first region. The ridge includes the second region.

In a multilayer ceramic capacitor, an intersection of an interface is defined by a second dielectric ceramic layer, a first internal electrode layer or a second internal electrode layer, and a third dielectric ceramic layer, on a plane including a length direction and a width direction, the second dielectric ceramic layer and the third dielectric ceramic layer include a near intersection region at or near the intersection, and an average particle size of dielectric particles in the near intersection region is smaller than average particle sizes of dielectric particles in the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer.

A method for manufacturing a multilayer ceramic electronic device includes punching out a ceramic sheet by one of left and right side surfaces of a laminated body so as to form a side margin part on the one of the left and right side surfaces of said laminated body; and punching out another ceramic sheet by another of the left and right side surfaces of the laminated body so as to form a side margin part on the another of the left and right side surfaces of said laminated body, thereby forming a ceramic main body having the laminated body and the pair of side margin parts that respectively cover the left and right side surfaces of the laminated body. The width W is greater than the length L in the multilayer ceramic electronic device.

A multilayer capacitor includes a body including a dielectric layer and first and second internal electrodes stacked on each other and having the dielectric layer interposed therebetween; a pair of first external electrodes respectively disposed on first and second corners of the body, which are not adjacent to each other, and connected to the first internal electrode; a pair of second external electrodes respectively disposed on third and fourth corners of the body, which are not adjacent to each other, and connected to the second internal electrode; and a reinforcing portion disposed on a surface of the body, not covered by at least one of the first and second external electrodes, and including a sintered ceramic body.

A ceramic electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode disposed on the body and connected to the internal electrode. The dielectric layer has a perovskite structure represented by a general formula ABO.sub.3 as a main phase, and includes a region in which Dy is solid solubilized. In the region in which the Dy is solid solubilized, an X-ray count of Dy solid-solubilized in an A-site of the perovskite structure measured by using Scanning Transmission Electron Microscopy-Energy Dispersive X-ray Spectroscopy (STEM-EDS) is AD, an X-ray count of Dy solid-solubilized in a B-site of the perovskite structure is BD, and an average value of AD/BD is 1.6 or more and 2.0 or less.

A ceramic electronic device includes a multilayer structure in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked. Each of the plurality of dielectric layers includes ceramic grains of a main component thereof expressed by (Ba.sub.1−x−yCa.sub.xSr.sub.y)(Ti.sub.1−zZr.sub.z)O.sub.3 (0<x≤0.2, 0≤y≤0.1, 0≤z≤0.1). D3<D1<D2 is satisfied when an average grain diameter of the ceramic grains of the main component of the plurality of dielectric layers in a section in which each two internal electrode layers is D1, an average grain diameter of the ceramic grains of the main component of first dielectric layers which are located at different height positions from the internal electrode layers is D2, an average grain diameter of the ceramic grains of the main component of second dielectric layers which are located at same height positions of the internal electrode layers is D3.

A ceramic electronic device includes a multilayer chip in which a dielectric layer and an internal electrode layer are alternately stacked. Concentration peaks of two or more types of metals different from a main component metal of the internal electrode layer exist at different positions in a stacking direction of the dielectric layer and the internal electrode layer, between the dielectric layer and the internal electrode layer.