A method for testing an integrated circuit (IC) using a nanoprobe, by using a scanning electron microscope (SEM) to register the nanoprobe to an identified feature on the IC; navigating the nanoprobe to a region of interest; scanning the nanoprobe over the surface of the IC while reading data from the nanoprobe; when the data from the nanoprobe indicates that the nanoprobe traverse a feature of interest, decelerating the scanning speed of the nanoprobe and performing testing of the IC. The scanning can be done at a prescribed nanoprobe tip force, and during the step of decelerating the scanning speed, the method further includes increasing the nanoprobe tip force.

A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

A method for testing an integrated circuit (IC) using a nanoprobe, by using a scanning electron microscope (SEM) to register the nanoprobe to an identified feature on the IC; navigating the nanoprobe to a region of interest; scanning the nanoprobe over the surface of the IC while reading data from the nanoprobe; when the data from the nanoprobe indicates that the nanoprobe traverse a feature of interest, decelerating the scanning speed of the nanoprobe and performing testing of the IC. The scanning can be done at a prescribed nanoprobe tip force, and during the step of decelerating the scanning speed, the method further includes increasing the nanoprobe tip force.

A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

In a method for obtaining the dielectric constant of a dielectric sheet, a modulation voltage is applied to a semiconductor capacitor and a first parallel plate capacitor to measure a first scanning capacitance microscopy signal. Then, the first parallel plate capacitor is replaced with a second parallel plate capacitor to measure a second scanning capacitance microscopy signal corresponding to the semiconductor capacitor and the second parallel plate capacitor. Finally, the second parallel plate capacitor is replaced with a third parallel plate capacitor to measure a third scanning capacitance microscopy signal corresponding to the semiconductor capacitor and the third parallel plate capacitor. Based on the scanning capacitance microscopy signals and dielectric constants and the equivalent physical thicknesses of the dielectric sheets of the first parallel plate capacitor and second parallel plate capacitor, the dielectric constant of the dielectric sheet of the third parallel plate capacitor is obtained.

In a method for obtaining the dielectric constant of a dielectric sheet, a modulation voltage is applied to a semiconductor capacitor and a first parallel plate capacitor to measure a first scanning capacitance microscopy signal. Then, the first parallel plate capacitor is replaced with a second parallel plate capacitor to measure a second scanning capacitance microscopy signal corresponding to the semiconductor capacitor and the second parallel plate capacitor. Finally, the second parallel plate capacitor is replaced with a third parallel plate capacitor to measure a third scanning capacitance microscopy signal corresponding to the semiconductor capacitor and the third parallel plate capacitor. Based on the scanning capacitance microscopy signals and dielectric constants and the equivalent physical thicknesses of the dielectric sheets of the first parallel plate capacitor and second parallel plate capacitor, the dielectric constant of the dielectric sheet of the third parallel plate capacitor is obtained.