G01R1/02

Battery cell full life tracking system

Certain embodiments are described that provide a method and computer readable media for testing battery cells. A unique identifier (e.g., barcode) is affixed to a battery cell which allows it to be tracked across separate tests as a cell, in a module, string, pack, etc. Using a GUI, the unique identifier is recorded in a database along with at least a battery cell manufacturer and a battery cell model. A designation of the particular tester channel or module or string location is entered into the database in association with the unique identifier. Test results of the first test are electronically transferred from the first tester to the database along with the corresponding channel designations.

Wireless test measurement

An installation test system has a control device and one or more hand-held test devices. The control device and the one or more hand-held devices are in wireless communication via respective communication systems. The control device performs typical pre-power tests including insulation testing and ground testing. There is at least one hand-held device dedicated to testing for residual current in circuit breakers and another hand-held device dedicated to testing for loop impedance. The control device records all test data and stores data in storage.

Testing system and method for testing of electrical connections
09759743 · 2017-09-12 · ·

A testing system includes a test machine, a plurality of probe sets, a data input device, a controller, a memory, and a data output device. The test machine has a platform for a DUT to be placed thereon, and a test arm which is movable relative to the platform. The probe sets are provided on the test machine with at least one probe set provided on the test arm to contact the DUT. The data input device is used to input information about the DUT. The controller is electrically connected to the test arm, the probe set on the test arm, and the data input device to move the test arm to a predetermined position according to the inputted information, and to make the probe set contact the DUT for electrical test. The memory saves electrical test result, which is outputted by the data output device.

ANALYSIS APPARATUS AND IMAGE CREATION METHOD
20210372944 · 2021-12-02 ·

An analysis apparatus, which is for analyzing a state of inspection of an object to be inspected having inspection target devices formed on the object to be inspected by using a probe card having probes formed on the probe card and configured to be brought into contact with the inspection target devices, includes a display part configured to display an image and an image creator configured to create the image to be displayed on the display part, wherein the image creator creates, based on a result of detecting at least one of heights of the probes in portions of the probe card and heights of the inspection target devices in portions of the inspection object, a height map image showing a distribution of the heights of at least one of the probes and the inspection target devices.

SWITCHING MATRIX SYSTEM AND OPERATING METHOD THEREOF FOR SEMICONDUCTOR CHARACTERISTIC MEASUREMENT
20220206040 · 2022-06-30 ·

The present disclosure provides a switching matrix system and an operating method thereof for semiconductor characteristic measurement. The switching matrix system is configured to: detect an assembly of at least one switching matrix module inserted into a plurality of slots of the switching matrix system; determine a user interface according to the assembly of the at least one switching matrix module inserted into the slots, wherein the user interface includes an operable object corresponding to the assembly; and provide the user interface.

Testing device

The present disclosure relates to a testing device comprising a bracket including a first groove and a second groove parallel to each other, wherein the first groove and the second groove run through an inner surface of the bracket perpendicularly to a thickness direction of the testing device; a plate assembly including a first plate and a second plate parallel to each other, wherein the first plate is disposed within the first groove and fits closely within the first groove along a length direction and a thickness direction of the testing device, the second plate is disposed within the second groove, with a gap present in the second groove along a length direction and/or a thickness direction of the testing device; a connector array including a plurality of connector assemblies disposed on the plate assembly in a predetermined pattern, wherein each of the plurality of connector assemblies is connected between the first plate and the second plate; and a displacing tool disposed on the bracket and/or the plate assembly and configured to displace the second plate relative to the first plate within the second groove along a length direction and/or a thickness direction of the testing device. The testing device may simulate various different axial deviations and/or angular deviations of the opposed printed circuit boards, and may be used to test the performance parameters such as low PIM, return loss and insertion loss between the printed circuit boards and the connectors under different axial deviations and/or angular deviations.

Testing device

The present disclosure relates to a testing device comprising a bracket including a first groove and a second groove parallel to each other, wherein the first groove and the second groove run through an inner surface of the bracket perpendicularly to a thickness direction of the testing device; a plate assembly including a first plate and a second plate parallel to each other, wherein the first plate is disposed within the first groove and fits closely within the first groove along a length direction and a thickness direction of the testing device, the second plate is disposed within the second groove, with a gap present in the second groove along a length direction and/or a thickness direction of the testing device; a connector array including a plurality of connector assemblies disposed on the plate assembly in a predetermined pattern, wherein each of the plurality of connector assemblies is connected between the first plate and the second plate; and a displacing tool disposed on the bracket and/or the plate assembly and configured to displace the second plate relative to the first plate within the second groove along a length direction and/or a thickness direction of the testing device. The testing device may simulate various different axial deviations and/or angular deviations of the opposed printed circuit boards, and may be used to test the performance parameters such as low PIM, return loss and insertion loss between the printed circuit boards and the connectors under different axial deviations and/or angular deviations.

TEST AND MEASUREMENT DEVICES, SYSTEMS AND METHODS ASSOCIATED WITH AUGMENTED REALITY

A test and measurement system can include a data store configured to store augmentation settings for dynamically augmenting a physical testing environment and a computing device coupled to the data store. The computing device can be configured to receive an input feed from the physical testing environment, create an augmentation image based on the augmentation settings and the input feed, and output the augmented image to be overlaid on the physical testing environment to augment a user's view of the physical testing environment.

Electronic component handling apparatus and electronic component testing apparatus

An electronic component handling apparatus handles a device under test (DUT). The electronic component handling apparatus includes: a set plate that holds a DUT container including a plurality of pockets each of which accommodates the DUT; a sensor that acquires three-dimensional shape data of the DUT container; and a processor that corrects the shape data based on an inclination of the set plate, extracts a height and an inclination of a predetermined region corresponding to the DUT in a first pocket among the pockets, from the shape data corrected by the processor, and determines an accommodation state of the DUT in the first pocket based on an extraction result obtained by the processor.

Enhancement of yield of functional microelectronic devices

Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.