Disclosed are a power characteristic measurement device, an image system including the power characteristic measurement device and an operating method of the image system, and the power characteristic measurement device may include a comparison circuit suitable for comparing impedance of an image sensor with impedance of a modeled image sensor, and an extraction circuit suitable for extracting the impedance of the image sensor according to a comparison result of the comparison circuit.

Disclosed are a power characteristic measurement device, an image system including the power characteristic measurement device and an operating method of the image system, and the power characteristic measurement device may include a comparison circuit suitable for comparing impedance of an image sensor with impedance of a modeled image sensor, and an extraction circuit suitable for extracting the impedance of the image sensor according to a comparison result of the comparison circuit.

Example implementations relate to circuits. For example, an implementation includes a detection circuit including a comparator circuit. The comparator circuit includes a first input terminal, a second input terminal, and an output terminal. The detection circuit also includes a reference voltage circuit to provide a set point voltage to the comparator circuit via the first input terminal. The detection circuit further includes a diode to reduce the set point voltage from a first magnitude to a second magnitude when the first magnitude is equal to or lower than a magnitude of the load voltage.

Example implementations relate to circuits. For example, an implementation includes a detection circuit including a comparator circuit. The comparator circuit includes a first input terminal, a second input terminal, and an output terminal. The detection circuit also includes a reference voltage circuit to provide a set point voltage to the comparator circuit via the first input terminal. The detection circuit further includes a diode to reduce the set point voltage from a first magnitude to a second magnitude when the first magnitude is equal to or lower than a magnitude of the load voltage.

According to aspects of the present disclosure there is provided an apparatus and method for sensing. The apparatus includes a sensor circuit which includes a first output terminal, a second output terminal and a sensor that is provided in a bridge circuit arrangement. The sensor circuit is configured such that a sensor measurement can be determined based on a voltage difference between first and second output terminals. The apparatus is configured so as to prevent a current from being able to flow from the first output terminal through the sensor circuit to the second output terminal.

According to aspects of the present disclosure there is provided an apparatus and method for sensing. The apparatus includes a sensor circuit which includes a first output terminal, a second output terminal and a sensor that is provided in a bridge circuit arrangement. The sensor circuit is configured such that a sensor measurement can be determined based on a voltage difference between first and second output terminals. The apparatus is configured so as to prevent a current from being able to flow from the first output terminal through the sensor circuit to the second output terminal.

During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.

During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.

A sampling circuit monitors a high voltage level in an electric vehicle drive. A resistor ladder receives a drive voltage to be sampled and provides sufficient isolation to allow use of low cost switching devices. An N-channel MOSFET is connected between the ladder and a reference resistance. A junction between the source terminal of the MOSFET and the reference resistance provides a sampled voltage output adapted to be input to an analog-to-digital converter. A discrete optocoupler has an output side with a collector and an emitter. The collector is coupled to the resistor ladder, and the emitter is connected to a gate terminal of the MOSFET and coupled to the ground reference by a load resistor.

A sampling circuit monitors a high voltage level in an electric vehicle drive. A resistor ladder receives a drive voltage to be sampled and provides sufficient isolation to allow use of low cost switching devices. An N-channel MOSFET is connected between the ladder and a reference resistance. A junction between the source terminal of the MOSFET and the reference resistance provides a sampled voltage output adapted to be input to an analog-to-digital converter. A discrete optocoupler has an output side with a collector and an emitter. The collector is coupled to the resistor ladder, and the emitter is connected to a gate terminal of the MOSFET and coupled to the ground reference by a load resistor.