Patent classifications
G01R17/10
MEASURING BRIDGE ARRANGEMENT WITH IMPROVED ERROR DETECTION
Disclosed is a measuring bridge arrangement containing: a measuring bridge comprising at least one first half bridge having a first measuring connection and a second half bridge having a second measuring connection; a reference voltage divider having at least one first and a second test connection; a differential amplifier having at least one first and a second amplifier input and at least one amplifier output, a voltage amplification, and having an output voltage working range. In the arrangement, the first amplifier input is wired to a first capacitor and the second amplifier input is wired to a second capacitor, and the amplifier inputs can be selectively connected to the measuring connections or to the test connections.
MEASURING BRIDGE ARRANGEMENT WITH IMPROVED ERROR DETECTION
Disclosed is a measuring bridge arrangement containing: a measuring bridge comprising at least one first half bridge having a first measuring connection and a second half bridge having a second measuring connection; a reference voltage divider having at least one first and a second test connection; a differential amplifier having at least one first and a second amplifier input and at least one amplifier output, a voltage amplification, and having an output voltage working range. In the arrangement, the first amplifier input is wired to a first capacitor and the second amplifier input is wired to a second capacitor, and the amplifier inputs can be selectively connected to the measuring connections or to the test connections.
Method for determining the resistance temperature characteristic of a ceramic glow plug
A method is described for determining the resistance temperature characteristic of a ceramic glow plug, wherein the glow plug is heated at a specified power, wherein before the heating it is first determined whether the glow plug is an aged glow plug, and then, if the glow plug has not been detected as an aged glow plug, the glow plug is heated at a first specified power and the resistance value thereby achieved is assigned to a temperature that is anticipated to be the final temperature when heating a factory-outlet glow plug at this first power, or if the glow plug has been detected as an aged glow plug, the glow plug is heated at a reduced power which is smaller than the first power, and the resistance value achieved thereby is assigned to the same temperature that is also anticipated when heating a factory-outlet glow plug at the first power.
Apparatus and Method for Sensing
According to aspects of the present disclosure there is provided an apparatus and method for sensing. The apparatus includes a sensor circuit which includes a first output terminal, a second output terminal and a sensor that is provided in a bridge circuit arrangement. The sensor circuit is configured such that a sensor measurement can be determined based on a voltage difference between first and second output terminals. The apparatus is configured so as to prevent a current from being able to flow from the first output terminal through the sensor circuit to the second output terminal.
Single-chip magnetic field sensor bridge
A single-chip magnetic field sensor bridge, comprising a substrate, a reference arm, a sensing arm, shielding structures, and wire bond pads is disclosed. The reference arm and the sense arm respectively comprise at least two rows/columns of reference element strings and sense element strings formed by electrically connecting one or more identical magnetoresistive sensing elements. The reference element strings and the sense element strings are alternately arranged. The magnetoresistive sensing elements are AMR, GMR or TMR sensing elements. The reference element strings are provided with shielding structures thereon, and the sensing element strings are located in gaps between two adjacent shielding structures. The shielding structures are arrays of elongated strips composed of permalloy or another soft ferromagnetic material. The sensors can be implemented as one of three different bridge structures, called a quasi-bridge, a half-bridge, or a full-bridge. This single-chip magnetic field sensor bridge has the advantages of small size, low cost, high sensitivity, small offset, good linearity, and good temperature stability.
Bottom leads chemical mechanical planarization for TMR magnetic sensors
A Wheatstone bridge array comprising a tunneling magnetoresistive (TMR) sensor and a method for manufacturing is disclosed. The bottom lead for the TMR sensor has a very small surface roughness due to not only chemical mechanical planarization (CMP) but also due to forming the bottom lead from multiple layers. The multiple layers include at least a bottom first metal layer and a top second metal layer disposed on the first metal layer. The second metal layer generally has a lower surface roughness than the first metal layer. Additionally, the second metal layer has a slower polishing rate. Therefore, not only does the second metal layer reduce the surface roughness simply be being present, but the slower polishing rate enables the top second metal film to be polished to a very fine surface roughness of less than or equal to ˜2 Angstroms.
AC Impedance Measurement Circuit with Calibration Function
The present invention discloses an AC impedance measurement circuit with a calibration function, which is characterized in that only one calibration impedance is needed, associated with a switch circuit. Based on the measurement results of the two calibration modes, an equivalent impedance of the switch circuit, circuit gain and phase offset can be calculated. Based on the above results, the equivalent impedance of the internal circuit is deducted from the measurement result of the measurement mode to accurately calculate an AC conductance and a phase of the AC conductance for impedance to be measured. In addition, by adjusting a phase difference between an input sine wave signal and a sampling clock signal, impedance of the same phase and impedance of the quadrature phase can be obtained, respectively, and the AC impedance and phase angle of the impedance to be measured can be calculated.
BRIDGE SENSOR DC ERROR CANCELLATION SCHEME
The disclosed techniques provide a number of technical benefits by providing a bridge sensor DC error cancellation scheme. In one embodiment, a system includes a piezoresistive Wheatstone bridge, a number of switches, and a non-overlapping clock. The system can mitigate noise and other errors by subtraction of the two differential outputs of the system between a first phase and a second phase of a clock input controlling the switches. In some embodiments, the system can also include differential programmable gain amplifiers and a multi-bit analog-to-digital converter. By providing a bridge sensor DC error cancellation scheme for producing an analog output, a system can be used to generate a stable digital output of at the analog-to-digital converter.
Gas Chromatograph (GC) detector to provide GC measurement in digital form
A Gas Chromatograph (GC) detector comprises a first circuit, a second circuit, a digital subtractor and a digital logic shared between one to many detector channels to provide a GC measurement in a digital form. The first circuit includes a first counter circuitry to provide a first counter output. The second circuit includes a second counter circuitry to provide a second counter output. The GC detector includes a digital subtractor to subtract the first counter output from the second counter output and provide a digital subtractor output. The GC detector further includes a digital logic shared between one to many detector channels to implement at least a portion of the first counter circuitry and the second counter circuitry. The digital logic to receive the digital subtractor output and provides the GC measurement in the digital form. The GC detector may be based on a Thermal Conductivity Detector (TCD) in which an integrator of a Sigma-Delta (Σ-Δ) A/D converter is eliminated and the Σ factor of the Sigma-Delta (Σ-Δ) A/D converter is accomplished in a digital form.
Semiconductor testkey pattern and test method thereof
The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns.