The peak comparator circuitry comprises a differential amplifier circuit having an output node to generate a differential amplifier output signal in response to an amplification of a difference of an input signal and a reference signal, and a comparator circuit having an output node to generate a comparator output signal. A feedback path of the peak comparator circuitry is arranged between the output node of the comparator circuit and the output node of the differential amplifier circuit. The proposed peak comparator circuitry allows for a low voltage supply, a low current consumption and a fast output validity.

The present application relates to the technical field of electronic circuits, and provides a gate detection circuit of an insulated gate bipolar transistor. The pulse shaping circuit is configured for shaping an input signal of a signal input device, and outputting a first square wave signal of a high level and a second square wave signal of a low level when the input signal is at the high level; and outputting a first square wave signal of the low level and a second square wave signal of the high level when the input signal is at the low level; the comparison circuit is configured for: comparing a first preset voltage with a voltage of a gate of the insulated gate bipolar transistor when the first square wave signal is at the high level, and outputting a low level when the first preset voltage is greater than the voltage of the gate of the insulated gate bipolar transistor; and comparing a second preset voltage with a voltage of a gate of the insulated gate bipolar transistor when the second square wave signal is at the high level, and outputting a low level when the second preset voltage is lower than the voltage of the gate of the insulated gate bipolar transistor; and the fault output circuit is configured for outputting a gate fault signal when the comparison circuit outputs the low level. The present application can detect the gate fault of the insulated gate bipolar transistor.

A detection circuit for the on-board direct current/direct current (DC/DC) ground wire and an on-board device are provided. The circuit includes a digital signal process (DSP) controller, a detection circuit, a standby circuit for an on-board DC/DC converter, and a power-supply negative wire for the on-board DC/DC converter. The detection circuit includes a comparator, a first conductive branch, a second conductive branch, a third conductive branch. In this way, the detection circuit is connected between the DSP controller and the standby circuit for the on-board DC/DC converter, and the detection circuit is connected between the DSP controller and the power-supply negative wire for the on-board DC/DC converter.

A battery system includes at least one battery pack including: a plurality of battery cells; a plurality of pre-charge resistors connected to one terminal of the at least one battery pack; a plurality of pre-charge switches of which one terminal is connected to the other terminal of a plurality of pre-charge resistors; a plurality of capacitors connected to the other terminal of a plurality of pre-charge switches; and a main control circuit that determines whether a plurality of pre-charge resistors are abnormal according to a result of comparing a sum of a plurality of branch currents calculated by using a pre-stored value of a plurality of resistances of the plurality of pre-charge resistors and the voltage of both terminals of a plurality of pre-charge resistors with a battery current flowing through at least one battery pack, when the first period has elapsed during the performing of the pre-charge operation.

A battery diagnosing technology capable of effectively diagnosing a state of a secondary battery using a charge and discharge signal extracted from the secondary battery, including memory to store a positive electrode reference profile and a negative electrode reference profile for charge or discharge of a reference battery, a voltage sensor to measure a voltage of a target battery during a charge or discharge process, and a processor to generate a plurality of charge and discharge measurement profiles based on voltages measured at a plurality of different time points, compare each of the generated charge and discharge measurement profiles with a simulation profile obtained from the positive and negative electrode reference profiles, and determine positive and negative electrode adjustment profiles for each of the generated charge and discharge measurement profiles so that an error between each charge and discharge measurement profile and the simulation profile is within a predetermined level.

In a voltage detection circuit, if a driving signal is provided from a control circuit to a drive target circuit that is one of a plurality of individual detection circuits, and a non-driving signal is provided from the control circuit to the other non-target circuits, switch portions of the non-target circuits are turned off to prevent a current from flowing through first transistors and second transistors of the non-target circuits, whereby generation of the output voltages in the non-target circuits is stopped, and a switch portion of the drive target circuit is turned on so as to allow a current to flow through a first transistor and a second transistor of the drive target circuit, whereby a voltage according to a voltage across both ends of an electricity storage cell corresponding to the drive target circuit is applied to an output conductive path.

A MEMS device may output a signal during operation that may include an in-phase component and a quadrature component. An external signal having a phase that corresponds to the quadrature component may be applied to the MEMS device, such that the MEMS device outputs a signal having a modified in-phase component and a modified quadrature component. A phase error for the MEMS device may be determined based on the modified in-phase component and the modified quadrature component.

A full voltage sampling circuit includes a main sampling circuit, an assist sampling circuit and a processing circuit. The main sampling circuit receives first and second input voltages, and outputs a first sampling signal according to the first and second input voltages. The first sampling signal represents a differential voltage which indicates a difference between the first input voltage and the second input voltage. The assist sampling circuit receives the first and second input voltages, and outputs a second sampling signal according to the first and second input voltages. The second sampling signal represents the differential voltage. The processing circuit is coupled to the main sampling circuit and the assist sampling circuit, and selects a larger one of currents or voltages of the first and second sampling signals as a sampling result to be outputted.

A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.

A detection circuit for detecting an external device with a specific resistance is provided. The detection circuit includes a first resistor, a second resistor, a first converter, a second converter, a device converter, a first current comparator, and a second current comparator. The first resistor has a first resistance. The second resistor has a second resistance. The first converter is configured to convert the first resistance into a first current. The second converter is configured to convert the second resistance into a second current. The device converter is configured to convert the specific resistance into a specific current. The first current comparator is configured to compare the specific current with the first current, and generate a first output signal. The second current comparator is configured to compare the specific current with the second current, and generate a second output signal.