Examples of operating an Intelligent Electronic Device (IED) during power swings, are described. In an example, voltage measurements for a phase is received and sampled. Root mean square (RMS) values of the voltage samples is calculated based on the voltage measurements. Delta quantities for each phase are calculated based on the RMS values. Each of the RMS values and delta quantities are associated with respective sampling instants. In response to a delta quantity being greater than a predefined threshold, a peak delta quantity is detected. A time interval between a sampling instant associated with the peak delta quantity and a sampling instant associated with a first delta quantity is determined. Based on a comparison of the time interval with a threshold time, a disturbance condition may be detected as a power swing and consequently, fault detection at the IED may be blocked.

Examples of operating an Intelligent Electronic Device (IED) during power swings, are described. In an example, voltage measurements for a phase is received and sampled. Root mean square (RMS) values of the voltage samples is calculated based on the voltage measurements. Delta quantities for each phase are calculated based on the RMS values. Each of the RMS values and delta quantities are associated with respective sampling instants. In response to a delta quantity being greater than a predefined threshold, a peak delta quantity is detected. A time interval between a sampling instant associated with the peak delta quantity and a sampling instant associated with a first delta quantity is determined. Based on a comparison of the time interval with a threshold time, a disturbance condition may be detected as a power swing and consequently, fault detection at the IED may be blocked.

A circuit arrangement for monitoring an alternating voltage signal includes a comparator configured to receive the alternating voltage signal or a signal obtained from the alternating voltage signal at a first comparator input and output a comparator signal at a comparator output. The circuit arrangement further includes a zero crossing detector configured to receive a reference signal or a signal obtained from the reference signal at a monitoring input and generate a detector signal at an output of the zero crossing detector. The circuit arrangement further includes a logic circuit including a first timing element connected downstream of the zero crossing detector for generating a first clock signal and a second timing element connected downstream of the zero crossing detector for generating a second clock signal.

Systems and methods are provided for improving the operation of a computer or other electronic device that utilizes root-mean-square (RMS) measurements, e.g., RMS current measurements, by reducing error in the RMS measurement. A series of measurement samples are received at a processor, which executes a noise-decorrelated RMS algorithm including: calculating a current-squared value for each measurement sample by multiplying the measurement sample by a prior measurement sample in the series (rather by simply squaring each measurement sample as in conventional techniques), summing the current-squared values, and calculating an RMS value based on the summed values. The processor may also execute a frequency-dependent magnitude correction filter to correct for frequency-dependent attenuation associated with the noise-decorrelated RMS algorithm. The calculated RMS value has a reduced error, particularly for lower-end current measurements, which may improve the operation of the computer or electronic device that utilizes the RMS value.

Systems and methods are provided for improving the operation of a computer or other electronic device that utilizes root-mean-square (RMS) measurements, e.g., RMS current measurements, by reducing error in the RMS measurement. A series of measurement samples are received at a processor, which executes a noise-decorrelated RMS algorithm including: calculating a current-squared value for each measurement sample by multiplying the measurement sample by a prior measurement sample in the series (rather by simply squaring each measurement sample as in conventional techniques), summing the current-squared values, and calculating an RMS value based on the summed values. The processor may also execute a frequency-dependent magnitude correction filter to correct for frequency-dependent attenuation associated with the noise-decorrelated RMS algorithm. The calculated RMS value has a reduced error, particularly for lower-end current measurements, which may improve the operation of the computer or electronic device that utilizes the RMS value.

A device that includes an adaptive acoustic detection circuit and an acoustic sensor device such as a microphone is described. The device includes in addition to the sensor a circuit configured to detect when an input stimulus to the sensor satisfies an adaptive threshold, and further configured to produce a signal upon detection that causes adjustment of performance of the device, wherein the adaptive threshold is a threshold value that varies over time in accordance with detected changes to sound of an environment in which the device is located.

A device that includes an adaptive acoustic detection circuit and an acoustic sensor device such as a microphone is described. The device includes in addition to the sensor a circuit configured to detect when an input stimulus to the sensor satisfies an adaptive threshold, and further configured to produce a signal upon detection that causes adjustment of performance of the device, wherein the adaptive threshold is a threshold value that varies over time in accordance with detected changes to sound of an environment in which the device is located.

In one example, an arc fault circuit interrupter (AFCI) is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist. A method for detecting an arc fault is also provided.

In one example, an arc fault circuit interrupter (AFCI) is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist. A method for detecting an arc fault is also provided.

A method and system measure a characteristic of a signal under test (SUT) using a signal measurement device. The method includes receiving and digitizing the first and second copies of the SUT through first and second input channels to obtain first and second digitized waveforms; repeatedly determining measurement values of the SUT characteristic in the first and second digitized waveforms to obtain first and second measurement values, which are paired in measurement value pairs; multiplying the first and second measurement values in each of the measurement value pairs to obtain measurement products; determining an average value of the measurement products to obtain an MSV of the measured SUT characteristic; and determine a square root of the MSV to obtain an RMS value of the measured SUT characteristic. The RMS value substantially omits variations not in the SUT, which are introduced by only one of the first and second input channels.