A power management circuit operable with group delay is provided. In embodiments disclosed herein, the power management circuit includes a voltage processing circuit configured to receive a first time-variant target voltage having a first group delay relative to a time-variant target voltage and a second time-variant target voltage having a second group delay relative to the time-variant target voltage. Accordingly, the voltage processing circuit generates a windowed time-variant target voltage higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a group delay tolerance window(s) defined by the first group delay and the second group delay. As a result, the power management circuit can generate a time-variant voltage based on the windowed time-variant target voltage to help a power amplifier to avoid amplitude clipping when amplifying an analog signal.

A circuit with a differential input configured to receive a differential analog input signal. The circuit also includes a common mode detection circuit, a primary signal circuit coupled, and a replica block. The circuit also includes a summer coupled to the output of the primary signal circuit and to an output of the replica block.

A circuit with a differential input configured to receive a differential analog input signal. The circuit also includes a common mode detection circuit, a primary signal circuit coupled, and a replica block. The circuit also includes a summer coupled to the output of the primary signal circuit and to an output of the replica block.

A circuit with a differential input configured to receive a differential analog input signal. The circuit also includes a common mode detection circuit, a primary signal circuit coupled, and a replica block. The circuit also includes a summer coupled to the output of the primary signal circuit and to an output of the replica block.

A circuit with a differential input configured to receive a differential analog input signal. The circuit also includes a common mode detection circuit, a primary signal circuit coupled, and a replica block. The circuit also includes a summer coupled to the output of the primary signal circuit and to an output of the replica block.

A system and a method is provided for the detection and capture, and in particular for an ultra high speed detection and capture, of transients in input voltages by an intelligent electronic device. The system and method detects transients for input voltages in either phase to phase or phase to neutral measurements and permits a user to set threshold levels for detecting transients in input voltages. In an embodiment, the system and method further provides a field programmable gate array as a controller for managing transient detection. The field programmable gate array includes a state machine for determining the state of the sampled signal with respect to a threshold level at a specified waveform sample period.

A system and a method is provided for the detection and capture, and in particular for an ultra high speed detection and capture, of transients in input voltages by an intelligent electronic device. The system and method detects transients for input voltages in either phase to phase or phase to neutral measurements and permits a user to set threshold levels for detecting transients in input voltages. In an embodiment, the system and method further provides a field programmable gate array as a controller for managing transient detection. The field programmable gate array includes a state machine for determining the state of the sampled signal with respect to a threshold level at a specified waveform sample period.

An apparatus and method for current peak detection. The apparatus includes a pulse laser diode array, a sense resistor, a capacitive voltage divider (CVD) electrically coupled to the pulse laser diode array, a first current rectifier, a second current rectifier, a first current peak detector, a second current peak detector, an analog-to-digital converter (ADC) operable to convert the analog outputs from each current peak detector to a digital output signal, and a digital signal processing (DSP) unit operable to detect, from the digital output signal, a current peak pulse at the top and the bottom of the sense resistor.

An apparatus and method for current peak detection. The apparatus includes a pulse laser diode array, a sense resistor, a capacitive voltage divider (CVD) electrically coupled to the pulse laser diode array, a first current rectifier, a second current rectifier, a first current peak detector, a second current peak detector, an analog-to-digital converter (ADC) operable to convert the analog outputs from each current peak detector to a digital output signal, and a digital signal processing (DSP) unit operable to detect, from the digital output signal, a current peak pulse at the top and the bottom of the sense resistor.

One embodiment provides an electronic control unit (ECU) for a vehicle. The ECU includes transceiver circuitry, voltage measurement circuitry and feature set circuitry. The transceiver circuitry is to at least one of send and/or receive a message. The voltage measurement circuitry is to determine at least one of a high bus line voltage (VCANH) value and/or a low bus line voltage (VCANL) value, for each zero bit of at least one zero bit of a received message. The received the message includes a plurality of bits. The feature set circuitry is to determine a value of at least one feature of a feature set based, at least in part, on at least one of a high acknowledge (ACK) threshold voltage (VthH) and/or a low ACK threshold voltage (VthL). The feature set includes at least one of an operating most frequently measured VCANH value (VfreqH2) of a number of VCANH values and/or an operating most frequently measured VCANL value (VfreqL2) of a number of VCANL values.