G01R23/02

PROCESSING SINEWAVE SIGNALS OF VARIABLE FREQUENCY IN A DEVICE WITH FIXED PROCESSING RATES

A method includes obtaining electrical measurements of an input signal of a power system. The electrical measurements are obtained at a sampling frequency and the input signal is indicative of an operating frequency of the power system. The method includes generating an intermediate signal from the input signal. The intermediate signal has a direct current (DC) component indicative of a magnitude and a phase of the input signal. The method includes filtering the intermediate signal using an adjustable length filter to obtain the magnitude and the phase of the input signal. The length of the adjustable length filter varies based at least in part on a period measurement of the power system.

PROCESSING SINEWAVE SIGNALS OF VARIABLE FREQUENCY IN A DEVICE WITH FIXED PROCESSING RATES

A method includes obtaining electrical measurements of an input signal of a power system. The electrical measurements are obtained at a sampling frequency and the input signal is indicative of an operating frequency of the power system. The method includes generating an intermediate signal from the input signal. The intermediate signal has a direct current (DC) component indicative of a magnitude and a phase of the input signal. The method includes filtering the intermediate signal using an adjustable length filter to obtain the magnitude and the phase of the input signal. The length of the adjustable length filter varies based at least in part on a period measurement of the power system.

Conversion rate control for analog to digital conversion
09841446 · 2017-12-12 · ·

A method, apparatus, and energy metering system obtains mains samples of a mains power line signal, performs non-white noise (NWN) filtering of the mains power line signal, obtains adjustable clock source samples of an adjustable clock signal of an adjustable clock oscillator, determines a difference based on the mains samples and the adjustable clock source samples, adjusts an adjustable clock source frequency of the adjustable clock oscillator based on the difference, and applies the adjustable clock source frequency to an analog to digital converter (ADC) to determine a conversion rate of the ADC.

Frequency Delta-Sigma Modulation Signal Output Circuit And Sensor Module
20230188158 · 2023-06-15 ·

A frequency delta-sigma modulation signal output circuit includes: a phase modulation circuit configured to generate n delay signals obtained by delaying a measurement target signal, n being an integer of 2 or more, and generate a phase modulation signal by randomly selecting one of the n delay signals in synchronization with the measurement target signal; and a frequency ratio digital conversion circuit configured to generate a frequency delta-sigma modulation signal using a reference signal and the phase modulation signal.

METHOD AND ELECTRONIC DEVICE FOR ESTIMATING FREQUENCIES OF MULTIPLE SINUSOIDS WHICH TRADES BIAS WITH VARIANCE

Accordingly embodiments herein disclose a method for estimating frequencies of multiple sinusoids by an electronic device (100). The method includes receiving a signal, where the signal comprises the multiple sinusoids. Further, the method includes estimating an initial frequency of each of the multiple sinusoids present in the received signal, determining that a first candidate parameter is less than zero, where the candidate parameter is a function of an estimated Signal-to-noise ratio (SNR) and an estimated threshold. Further, the method includes performing zero-padding on the received signal. Further, the method includes re-estimating frequencies obtained from zero-padded version of the received signal. Further, the method includes validating the re-estimated frequencies obtained from zero-padded version of the received signal based on validation criteria. Further, the method includes predicting the re-estimated frequencies or the initial frequencies as optimal frequencies based on the validation. Further, the method includes refining re-estimated frequencies using iterative filtering.

METHOD AND ELECTRONIC DEVICE FOR ESTIMATING FREQUENCIES OF MULTIPLE SINUSOIDS WHICH TRADES BIAS WITH VARIANCE

Accordingly embodiments herein disclose a method for estimating frequencies of multiple sinusoids by an electronic device (100). The method includes receiving a signal, where the signal comprises the multiple sinusoids. Further, the method includes estimating an initial frequency of each of the multiple sinusoids present in the received signal, determining that a first candidate parameter is less than zero, where the candidate parameter is a function of an estimated Signal-to-noise ratio (SNR) and an estimated threshold. Further, the method includes performing zero-padding on the received signal. Further, the method includes re-estimating frequencies obtained from zero-padded version of the received signal. Further, the method includes validating the re-estimated frequencies obtained from zero-padded version of the received signal based on validation criteria. Further, the method includes predicting the re-estimated frequencies or the initial frequencies as optimal frequencies based on the validation. Further, the method includes refining re-estimated frequencies using iterative filtering.

Precision frequency monitor
09813045 · 2017-11-07 · ·

A precision frequency monitor provides a precision frequency monitor value (PFM) indicative of the precision of the frequency or period of an input reference signal. A first averaging module is responsive to the input reference signal to find an average frequency or period during successive predetermined time periods defining operational cycles. A second averaging module is responsive to an output of the first averaging module to average the output of the first averaging module over N operational cycles, where N is an integer, and output an updated PFM value every N operational cycles. An infinite impulse response (IIR) filter is responsive to the output of the first averaging module to filter the output of the first averaging module to output interim updated PFM values within each sequence of N operational cycles.

Precision frequency monitor
09813045 · 2017-11-07 · ·

A precision frequency monitor provides a precision frequency monitor value (PFM) indicative of the precision of the frequency or period of an input reference signal. A first averaging module is responsive to the input reference signal to find an average frequency or period during successive predetermined time periods defining operational cycles. A second averaging module is responsive to an output of the first averaging module to average the output of the first averaging module over N operational cycles, where N is an integer, and output an updated PFM value every N operational cycles. An infinite impulse response (IIR) filter is responsive to the output of the first averaging module to filter the output of the first averaging module to output interim updated PFM values within each sequence of N operational cycles.

Frequency synthesizer output cycle counter including ring encoder

A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

Frequency synthesizer output cycle counter including ring encoder

A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.