A receiver with a power detecting function for a pulsed signal is provided. Said receiver comprises an accumulator for accumulating samples of the respective power of the corresponding signal over time. In this context, the respective accumulation length is a window being based on the pulse length of the corresponding signal. Furthermore, the receiver may additionally comprise an output for outputting several windows and a maximum detector. In this context, the maximum detector is configured to determine a maximum power value of the several windows.

The invention relates to devices and methods of characterising a single unknown pulse signal. They create multiple replica of the original that may be more reliably measured, by dividing the signal through nodes and using different signal pathways that may apply a temporal delay. The device and methods have multiple fields of application, most notably with the internal confinement fusion industry.

The invention relates to devices and methods of characterising a single unknown pulse signal. They create multiple replica of the original that may be more reliably measured, by dividing the signal through nodes and using different signal pathways that may apply a temporal delay. The device and methods have multiple fields of application, most notably with the internal confinement fusion industry.

A method for measuring a power-on reset time includes: detecting a power supply pin voltage of a chip, and recording a time point at which the power supply pin voltage reaches a preset voltage as a first time point; detecting an output signal of a preset pin of the chip, and recording a time point at which the preset pin completes a pulse output for a first time after the chip is powered on, as a second time point, and recording a time point the preset pin completes a pulse output for a second time, as a third time point; wherein widths of the pulse output for the first time and for the second time are the same; and computing the power-on reset time of the chip according to the first time point, the second time point and the third time point.

A method for measuring a power-on reset time includes: detecting a power supply pin voltage of a chip, and recording a time point at which the power supply pin voltage reaches a preset voltage as a first time point; detecting an output signal of a preset pin of the chip, and recording a time point at which the preset pin completes a pulse output for a first time after the chip is powered on, as a second time point, and recording a time point the preset pin completes a pulse output for a second time, as a third time point; wherein widths of the pulse output for the first time and for the second time are the same; and computing the power-on reset time of the chip according to the first time point, the second time point and the third time point.

A method for recognizing an electrical oscillation in an electrical power supply system, in which an electrical oscillation variable is determined for at least one measuring point in the power supply system. Parameters of an electrical oscillation are calculated on the basis of a time curve of the oscillation variable for the at least one measuring point, and the presence and type of an electrical oscillation is deduced using the parameters. To be able to provide correct parameters for assessing the oscillation in a timely fashion after the start of the oscillation, it is proposed that the number of those successive values of the oscillation variable from which the parameters of the electrical oscillation are calculated is adapted dynamically to the sequence of values of the oscillation variable.

Various implementations described herein are directed to a device having alarm circuitry that receives a clock signal and provides alarm chain signals based on the clock signal. The device may include delay chain circuitry that receives the alarm chain signals from the alarm circuitry and provides delay chain signals. The device may include output circuitry that receives the delay chain signals from the delay chain circuitry and provides an alarm control signal based on the delay chain signals.

A system and a method is provided for the detection and capture, and in particular for an ultra high speed detection and capture, of transients in input voltages by an intelligent electronic device. The system and method detects transients for input voltages in either phase to phase or phase to neutral measurements and permits a user to set threshold levels for detecting transients in input voltages. In an embodiment, the system and method further provides a field programmable gate array as a controller for managing transient detection. The field programmable gate array includes a state machine for determining the state of the sampled signal with respect to a threshold level at a specified waveform sample period.

A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.

First and second pulse height detection circuits output pulse height detection signals which rise when a detection pulse obtained from a radiation detector becomes greater than a lower threshold Lsh or an upper threshold Hsh, and fall when the detection pulse is smaller than the lower threshold Lsh or the upper threshold Hsh. Next, first and second rising and falling detection circuits detect rising and falling edges of the pulse height detection signals from the first and second pulse height detection circuits in synchronization with a clock pulse from a crystal oscillator, and a combining circuit outputs a signal corresponding to the detection pulse that is within a range between the lower threshold Lsh and the upper threshold Hsh by combining both outputs from the first and second rising and falling detection circuits, in synchronization with the clock pulse.