In the field of communications assemblies, particularly those arising in connection with high voltage direct current (HVDC) power converters, there is provided a communications assembly (10) that comprises a first module (12) which is arranged in operative communication with a second module (14A, 14B, 14C, 14D, 14E, 14F, 14G, 14H) via a communication conduit (16A, 16B, 16C, 16D, 16E, 16F, 16G, 16H). At least one of the first module (12) and the second module (14A, 14B, 14C, 14D, 14E, 14F, 14G, 14H) have a receiver (24) that includes a squelch filter (26) which is configured to operate in a first normal mode and a second test mode. The squelch filter (26) normally operates in the first normal mode to suppress a signal output (28) from the receiver (24) when the strength of an input signal (30) received by the receiver (24), via the communication conduit (16A, 16B, 16C, 16D, 16E, 16F, 16G, 16H), falls below a normal threshold. The squelch filter (26) selectively operates in the second test mode to suppress the signal output (28) from the receiver (24) when the strength of the input signal (30) received by the receiver (24), via the communication conduit (16A, 16B, 16C, 16D, 16E, 16F, 16G, 16H), falls below a test threshold higher than the normal threshold. When the squelch filter (26) is operating in the second test mode, a signal output (28) from the receiver (24) indicates a signal margin in the communication conduit (16A, 16B, 16C, 16D, 16E, 16F, 16G, 16H) that is at least equal to the difference between the test threshold and the normal threshold.

Noise injection systems and methods for conducting power noise susceptibility tests on memory systems, including solid state drives. A noise injection system comprises a power selector to deliver a voltage at a first or second level according to a frequency level indicated by a frequency select signal; a noise signal relay to receive a frequency noise signal and to deliver a low or high frequency noise component of the frequency noise signal according to the frequency level of the frequency select signal; and an amplification assembly, responsive to the frequency select signal and which receives the first or second level voltage based on the frequency level of the frequency select signal, receives and amplifies the high frequency noise component when the frequency select signal indicates a high frequency level, and receives and amplifies the low frequency noise component when the frequency select signal indicates a low frequency level.

Noise injection systems and methods for conducting power noise susceptibility tests on memory systems, including solid state drives. A noise injection system comprises a power selector to deliver a voltage at a first or second level according to a frequency level indicated by a frequency select signal; a noise signal relay to receive a frequency noise signal and to deliver a low or high frequency noise component of the frequency noise signal according to the frequency level of the frequency select signal; and an amplification assembly, responsive to the frequency select signal and which receives the first or second level voltage based on the frequency level of the frequency select signal, receives and amplifies the high frequency noise component when the frequency select signal indicates a high frequency level, and receives and amplifies the low frequency noise component when the frequency select signal indicates a low frequency level.

An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

A method for determining a noise shaped quantized parameter contributing to generation of an output signal comprises estimating an error within the output signal using a quantization of the parameter and a quantization of a further parameter contributing to generation of the output signal. The quantization of the parameter is used as the noise shaped quantized parameter according to a selection criterion.

A method for determining a noise shaped quantized parameter contributing to generation of an output signal comprises estimating an error within the output signal using a quantization of the parameter and a quantization of a further parameter contributing to generation of the output signal. The quantization of the parameter is used as the noise shaped quantized parameter according to a selection criterion.

A high-frequency noise detection antenna is provided with a fine coaxial line that includes a center conductor, an insulator provided so as to surround the whole periphery of the center conductor, and a ground shield provided so as to surround the whole periphery of the insulator, and in which a tip of the center conductor is exposed so as to protrude from the end of the insulator and the end of the ground shield, and an exposed ground shield provided so as to protrude from the end of the ground shield and surround a part in a circumferential direction of an exposed portion from which the center conductor protrudes.

A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.