A method for determining an emission coefficient of a device under test (DUT) using a test circuit comprises coupling a parameter measurement circuit associated with the test circuit to an input pin associated with the DUT, wherein the input pin is coupled to a diode element within the DUT and performing voltage and current measurements associated with the input pin using the parameter measurement circuit. In some embodiments, the method further comprises determining a plurality of contact resistance values respectively based on the voltage and current measurements and an emission coefficient estimate using a contact resistance estimation circuit; and determining an emission coefficient associated with the DUT based on the determined plurality of contact resistance values using an emission coefficient determination circuit.

A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.

The invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and alignment carriage that holds a wafer handling robot, a wafer rotation pre-alignment assembly, a wafer alignment assembly, a wafer front opening unified pod (FOUP), and a wafer camera assembly; and a robot that moves the wafer handling and alignment carriage to and from each test site. Each test site contains a wafer probe card assembly and a floating chuck. In use, wafers are loaded from a front opening FOUP into a wafer buffer FOUP from which wafers are retrieved by the wafer handling and alignment assembly. The robot positions the wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly in front of and inside a given test site and aligns the wafer to be tested with the probe card inside the test site using the floating chuck.

A method of testing an integrated circuit of a device is described. Air is allowed through a fluid line to modify a size of a volume defined between the first and second components of an actuator to move a contactor support structure relative to the apparatus and urge terminals on the contactor support structure against contacts on the device. Air is automatically released from the fluid line through a pressure relief valve when a pressure of the air in the fluid line reaches a predetermined value. The holder is moved relative to the apparatus frame to disengage the terminals from the contacts while maintaining the first and second components of the actuator in a substantially stationary relationship with one another. A connecting arrangement is provided including first and second connecting pieces with complementary interengaging formations that restricts movement of the contactor substrate relative to the distribution board substrate in a tangential direction.

The present invention relates to a state of charge (SOC) management system of an energy storage device, the system comprising at least one energy storage device, wherein the SOC management system of the energy storage device manages SOC of the energy storage device by performing P-f (active power-frequency) droop control on the basis of a droop coefficient, a reference frequency, and a dead band, which determine the output of each energy storage device.

Example devices and methods for compensating for monitoring a surge protection device are provided. In some embodiments, a device is configured to couple to a surge protection device. The device comprises a processor that is capable of sending a DC current signal. A serial data interface is electrically connected to the processor and includes at least one shift register. The device also comprises a multiplexer coupled to the serial data interface. The serial data interface is operable to direct the DC current through the multiplexer. The device also comprises an analog to digital converter (optionally embedded within the processor) that is operable to output a digital signal corresponding to a voltage induced by the DC current signal. Returned DC signals represent surge protection device's health and a multitude of other surge module information.

A semiconductor device includes first and second pads separated from each other, first and second test elements connected to the first and second pads and connected to each other in parallel between the first and second pads, a first diode connected to the first test element in series, and a second diode connected to the second test element in series.

The present disclosure relates to a method for estimating parameters of a junction of a power semi-conductor element comprising: •—Detecting at least one stable on-line operating condition through measurements (2, 3, 4) of Von, Ion, Tc on a semi-conductor module (1) where Ion is a current for which the on-state voltage Von of the semi-conductor is sensitive to the temperature and Tc is the temperature of the casing of said semi-conductor element; •—Measuring and storing at least one parameter set Von, Ion, Tc of said at least one stable operating condition; •—in a calculating unit (52), providing calculations for minimizing the error between a junction temperature estimation Tj of an electrical model Tj=F(Von, Ion, θelec) comprising a first set of unknown parameters θelec and another junction temperature estimation Tjmod of a loss/thermal model Tj=G(lon, Tc, θ mod) comprising a second set of unknown parameters θ mod and obtaining at least one set of parameters θelec and at least one parameter θ mod providing minimization of said error; •—providing the calculated value of Tj with at least one of the calculated parameters sets θelec and/or θ mod and the measured Von, Ion, Tc; •—Storing the at least one parameters set θelec and/or θ mod and/or Tj.

An inspection device comprising: a plurality of plungers; and a connection part electrically connecting at least some of the plungers of the plurality of plungers to each other.

A light emitting diode (LED) module includes a substrate layer including an active area and a non-active area excluding the active area, at least one wiring layer provided on the substrate layer, and a test pad connected to the at least one wiring layer and provided in the non-active area.