Patent classifications
G01R31/50
Apparatus for Detecting Defect of Electric Power System
An apparatus for detecting a defect of an electric power system according to one embodiment of the present disclosure includes a first state signal output unit for outputting a first state signal corresponding to a magnetic force generated at a periphery of a line, a second state signal output unit for outputting a second state signal based on a magnitude of a line current and an increase ratio thereof, and a determination unit for determining whether the electric power system is defective or not based on the first state signal and the second state signal.
Optimization of integrated circuit reliability
A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.
Testing systems and methods
A system of the present disclosure has a host testing device having a first wireless transceiver and having host testing device logic configured to transmit a test command via the first wireless transceiver. Additionally, the system has a remote testing device coupled to a system component. The remote testing device has a second wireless transceiver and remote testing device logic that receives the test command from the host testing device and executes the test command on the system component.
Testing systems and methods
A system of the present disclosure has a host testing device having a first wireless transceiver and having host testing device logic configured to transmit a test command via the first wireless transceiver. Additionally, the system has a remote testing device coupled to a system component. The remote testing device has a second wireless transceiver and remote testing device logic that receives the test command from the host testing device and executes the test command on the system component.
SYSTEM FOR CHECKING THE ELECTRICAL INSULATION IN CONVERTERS FOR ELECTRIC CARS
A system for checking the electrical insulation in converters for electric cars comprises at least one voltage generator connected to at least one line to be monitored of a high-voltage converter for electric vehicles and connected to the ground of said converter, and at least one current detection unit operatively connected to said voltage generator and configured to detect any current possibly present on the voltage generator and to generate a warning signal in the event of detection of the current.
MAINTAINING CONNECTIVITY INFORMATION FOR METERS AND TRANSFORMERS LOCATED IN A POWER DISTRIBUTION NETWORK
Methods for verifying and updating connectivity information in a geographic information system may consider location information for meters and transformers and voltage data obtained by the meters. Meters that are incorrectly associated with a transformer may be flagged and candidate transformers may be evaluated to identify a correct association. The analysis may consider voltage data from multiple meters to determine correlation values. Correlation values or confidence factors may be used to identify a transformer for the correct association.
MAINTAINING CONNECTIVITY INFORMATION FOR METERS AND TRANSFORMERS LOCATED IN A POWER DISTRIBUTION NETWORK
Methods for verifying and updating connectivity information in a geographic information system may consider location information for meters and transformers and voltage data obtained by the meters. Meters that are incorrectly associated with a transformer may be flagged and candidate transformers may be evaluated to identify a correct association. The analysis may consider voltage data from multiple meters to determine correlation values. Correlation values or confidence factors may be used to identify a transformer for the correct association.
DETECTING A FAILURE OF A PHASE IN A GRID FOR INVERTERS HAVING A FREQUENCY DETECTION IN AN INTERMEDIATE DC VOLTAGE LINK
A detection of a failure of a phase (as a method and apparatus) in a system—supplied by multiple phases—including a DC link (5) is suggested. A rectified voltage (10) of the DC link (5) pulses at a multiple of the mains frequency as a fundamental wave. The rectified voltage (10) is filtered for detecting a signal component at the double frequency of the mains frequency (12). The rectified voltage (10) is also “filtered” for detecting an average link voltage (14). A ratio signal (17) is formed as a ratio of the average link voltage (14) to the signal component at the double frequency of the mains frequency (12). An error detection signal (19) results from a comparison of the ratio signal (17) with an error threshold (20).
DIAGNOSTIC CIRCUITRY FOR POWERED SENSOR MULTIPLE UNIQUE FAULTS DIAGNOSTICS AND RESISTIVE FAULT TOLERANT INTERFACE TO MICROPROCESSOR
A sensing system includes circuitry having a diagnostic interface for a powered sensor. Responsive to sensing signals, the circuitry is operable to produce a DC level that is defined by operating or fault conditions. The fault conditions include an open voltage supply, an open sensor power return signal, open communication signal(s), series resistance in a communication signal, fault resistance to ground on the communication signal and fault resistance to a voltage source on the communication signal. The circuitry includes a fault tolerant interface between a wire harness at an output of the powered sensor and a digital input port of a microprocessor for the purpose of un-ambiguous fault detection when distortion of sensor information occurs or when loss of sensor information occurs, and wherein the microprocessor diagnoses a fault as defined by the DC level of the analog signal monitored at the communication signal input to the microprocessor.
SYSTEM AND METHOD OF TESTING SINGLE DUT THROUGH MULTIPLE CORES IN PARALLEL
The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.