A signal detecting circuit of a micro switch includes a first terminal, a second terminal, a third terminal and a micro controller. The first terminal has two ends that are respectively connected to a normally closed terminal of the micro switch and a resistor. The second terminal has two ends that are respectively connected to a normally opened terminal of the micro switch and a ground. The third terminal is connected to a common terminal of the micro switch. The micro controller has two ends that are respectively connected to the first terminal and the third terminal. When an elastic plate of the micro switch is pressed down, the common terminal is connected to the normally opened terminal. When the elastic plate of the micro switch is released, the common terminal is connected to the normally closed terminal.

A signal detecting circuit of a micro switch includes a first terminal, a second terminal, a third terminal and a micro controller. The first terminal has two ends that are respectively connected to a normally closed terminal of the micro switch and a resistor. The second terminal has two ends that are respectively connected to a normally opened terminal of the micro switch and a ground. The third terminal is connected to a common terminal of the micro switch. The micro controller has two ends that are respectively connected to the first terminal and the third terminal. When an elastic plate of the micro switch is pressed down, the common terminal is connected to the normally opened terminal. When the elastic plate of the micro switch is released, the common terminal is connected to the normally closed terminal.

This verification processing device is provided with: an inspection unit that performs model inspection on an inspection target model including a plurality of elements; a selection unit that selects at least one of the plurality of elements included in a counterexample outputted as a result of the model inspection; and an exclusion history generation unit that generates exclusion history information indicating an exclusion frequency for each of the plurality of elements. The inspection unit further performs another model inspection on the inspection target model obtained by excluding the selected element. When another counterexample has been outputted as a result of another model inspection, the exclusion history generation unit increases the exclusion frequency of the selected element and updates the exclusion history information. The selection unit selects an element that is high in the exclusion frequency, on the basis of the exclusion history information.

A ground fault circuit interrupter is provided, including a main control chip, a tripping unit and a self-test detection unit, wherein the tripping unit is connected with the self-test detection unit at a detection point and coupled with a load circuit; the self-test detection unit is coupled with the main control chip, and configured to detect a signal at the detection point and output the signal to the main control chip; the main control chip is coupled with the self-test detection unit, and configured to in a self-test state, simulate a circuit fault, perform self-test, and determine whether the circuit fault could be detected and an alarm signal response to the circuit fault is generated, based on the signal. A self-test function and alarm function response to a circuit fault in a ground fault circuit interrupter can be tested during a final test of production.

A ground fault circuit interrupter is provided, including a main control chip, a tripping unit and a self-test detection unit, wherein the tripping unit is connected with the self-test detection unit at a detection point and coupled with a load circuit; the self-test detection unit is coupled with the main control chip, and configured to detect a signal at the detection point and output the signal to the main control chip; the main control chip is coupled with the self-test detection unit, and configured to in a self-test state, simulate a circuit fault, perform self-test, and determine whether the circuit fault could be detected and an alarm signal response to the circuit fault is generated, based on the signal. A self-test function and alarm function response to a circuit fault in a ground fault circuit interrupter can be tested during a final test of production.

Techniques are provided for detecting a fault across a pair of lines. Pulse power is applied across the pair of lines. The pulse power comprises alternating pulse on-time intervals and pulse off-time intervals. During a pulse off-time interval, a resistor is connected across the pair of lines and then disconnected when a voltage across the pair of lines reaches a first droop percentage in a first period of time. After disconnecting the resistor, it is determined whether the voltage across the pair of lines droops at least a second droop percentage within a second period of time that begins after the first period of time. Occurrence of a line-to-line fault across the pair of lines is determined when the voltage across the pair of lines droops by at least the second droop percentage or more within the second period of time.

A method for abnormality detection in an energy unit includes passively detecting an abnormality in an energy unit by detecting electromagnetic radiation generated by the abnormality, the energy unit comprising at least one of an electrical energy unit and an electrochemical energy unit. A method for detecting an abnormality in an energy unit includes (a) applying a signal to the energy unit, (b) performing a plurality of measurements, at a respective plurality of different locations within the energy unit, of a response of the energy unit to the signal, and (c) processing the plurality of measurements to identify the abnormality.

An apparatus and a method for controlling an inverter are disclosed. A method, according to one embodiment of the present disclosure, receives an operation command for an inverter, outputs a first PWM control signal, to an inverter unit, such that the inverter unit outputs at least one among a plurality of valid vectors for the diagnosis of a short circuit of the output of the inverter, and blocks the output of the inverter if a short circuit current of the inverter is detected.

A fault protection arrangement may include a neutral grounding resistor, the neutral grounding resistor comprising a ground end and a non-ground end. The fault protection arrangement may include a neutral grounding resistance monitor assembly, coupled to the neutral grounding resistor, where the neutral grounding resistance monitor assembly includes a sense circuit, coupled to the ground end of the neutral grounding resistor; and an injection signal generator, arranged to generate a frequency of 240 Hz or greater.

A fault protection arrangement may include a neutral grounding resistor, the neutral grounding resistor comprising a ground end and a non-ground end. The fault protection arrangement may include a neutral grounding resistance monitor assembly, coupled to the neutral grounding resistor, where the neutral grounding resistance monitor assembly includes a sense circuit, coupled to the ground end of the neutral grounding resistor; and an injection signal generator, arranged to generate a frequency of 240 Hz or greater.