In a method of correcting a design layout of a semiconductor device, misaligned values of a portion of points of a target pattern of each of a plurality of regions of interest in a semiconductor device fabricated based on an original layout are measured, misaligned values of unmeasured points of the target pattern are estimated by using an artificial neural network trained based on the measured misaligned values of the portion of points, and a target layout of the semiconductor device is generated by using the estimated misaligned values.

Methods and apparatus for pattern matching and classification are disclosed. In one example of the disclosed technology, a method of performing pattern matching according to a puzzle-matching the methodology includes analyzing an original source layout pattern and determining a signature for the original source layout pattern. A target layout is scanned to search for one or more portions of the target layout that have a signature that matches or is similar to the signature of the original source pattern. Similar patterns are searched based on a signature comparison of the source pattern and the target layout. In some examples of the disclosed technology, it is possible to match partial context to the original source pattern. In some examples, matches can be made in the target layout for different orientations of layout.

Methods and apparatus for pattern matching and classification are disclosed. In one example of the disclosed technology, a method of performing pattern matching according to a puzzle-matching the methodology includes analyzing an original source layout pattern and determining a signature for the original source layout pattern. A target layout is scanned to search for one or more portions of the target layout that have a signature that matches or is similar to the signature of the original source pattern. Similar patterns are searched based on a signature comparison of the source pattern and the target layout. In some examples of the disclosed technology, it is possible to match partial context to the original source pattern. In some examples, matches can be made in the target layout for different orientations of layout.

Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a first voltage supply having the first supply voltage.

An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a first voltage supply having the first supply voltage.

A layout geometry of a lithographic mask is received. The layout geometry is partitioned into feature images, for example as selected from a library. The library contains predefined feature images and their corresponding precalculated mask 3D (M3D) filters. The M3D filter for a feature image represents the electromagnetic scattering effect of that feature image for a given source illumination. The mask function contribution from each of the feature images is calculated by convolving the feature image with its corresponding M3D filter. The mask function contributions are combined to determine a mask function for the lithographic mask illuminated by the source illumination.

A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.