A semiconductor device may include a substrate including a first logic cell and a second logic cell, which are adjacent to each other in a first direction and shares a cell border, a first metal layer on the substrate, the first metal layer including a power line, which is disposed on the cell border to extend in a second direction crossing the first direction and has a center line parallel to the second direction, and a second metal layer on the first metal layer. The second metal layer may include a first upper interconnection line and a second upper interconnection line, which are provided on each of the first and second logic cells. The first upper interconnection line may extend along a first interconnection track and the first direction. The second upper interconnection line may extend along a second interconnection track and in the first direction.

Various examples of integrated circuit layouts with line-end extensions are disclosed herein. In an example, a method includes receiving an integrated circuit layout that contains: a first and second set of shapes extending in parallel in a first direction, wherein a pitch of the first set of shapes is different from a pitch of the second set of shapes. A cross-member shape is inserted into the integrated circuit layout that extends in a second direction perpendicular to the first direction, and a set of line-end extensions is inserted into the integrated circuit layout that extend from each shape of the first set of shapes and the second set of shapes to the cross-member shape. The integrated circuit layout containing the first set of shapes, the second set of shapes, the cross-member shape, and the set of line-end extensions is provided for fabricating an integrated circuit.

Various examples of integrated circuit layouts with line-end extensions are disclosed herein. In an example, a method includes receiving an integrated circuit layout that contains: a first and second set of shapes extending in parallel in a first direction, wherein a pitch of the first set of shapes is different from a pitch of the second set of shapes. A cross-member shape is inserted into the integrated circuit layout that extends in a second direction perpendicular to the first direction, and a set of line-end extensions is inserted into the integrated circuit layout that extend from each shape of the first set of shapes and the second set of shapes to the cross-member shape. The integrated circuit layout containing the first set of shapes, the second set of shapes, the cross-member shape, and the set of line-end extensions is provided for fabricating an integrated circuit.

A pattern layout design method includes performing optical proximity correction (OPC) for a mask layout, thereby creating a corrected layout. Creation of the corrected layout includes creating a first corrected layout through grid snapping for an oblique edge of a mask layout designed on a grid layout, and performing optical proximity correction (OPC) for the first corrected layout, thereby creating a second corrected layout. Creation of the first corrected layout includes creating a first divisional point for the oblique edge or a residual edge, and shifting the first divisional point to one of four reference points adjacent to the first divisional point, thereby creating a first varied divisional point.

A method includes grouping, in a first layout, pattern regions which have duplicate layout patterns including weak regions as a group, calculating defect probabilities of the pattern regions, respectively, calculating a defect frequency and a defect rate of the group based on the defect probabilities of the pattern regions, predicting a degree of defects of a second layout of the pattern regions, based on the defect frequency and the defect rate, and performing an extreme ultraviolet (EUV) lithography process on a substrate, based on the second layout. The defect probabilities are calculated by performing an optical proximity correction (OPC) simulation on the pattern region, calculating a stochastic variation of a linewidth of a simulation pattern in the weak region as a Gaussian distribution, and defining a threshold linewidth, which is used as a reference of the random defect, in the Gaussian distribution.

A method includes grouping, in a first layout, pattern regions which have duplicate layout patterns including weak regions as a group, calculating defect probabilities of the pattern regions, respectively, calculating a defect frequency and a defect rate of the group based on the defect probabilities of the pattern regions, predicting a degree of defects of a second layout of the pattern regions, based on the defect frequency and the defect rate, and performing an extreme ultraviolet (EUV) lithography process on a substrate, based on the second layout. The defect probabilities are calculated by performing an optical proximity correction (OPC) simulation on the pattern region, calculating a stochastic variation of a linewidth of a simulation pattern in the weak region as a Gaussian distribution, and defining a threshold linewidth, which is used as a reference of the random defect, in the Gaussian distribution.

A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

A method for correcting a semiconductor mask pattern includes steps as follows: A pattern to be corrected in the semiconductor mask pattern is divided into a plurality of sub-blocks that are symmetrical to and coincide with each other. Then, an optical proximity correction (OPC) step is performed on one of the plurality of sub-blocks to obtain a modified template. At least one copy template is generated according to the modified template corresponding to the other ones of the plurality of sub-blocks. The modified template and the at least one copy template are spliced to form a correcting pattern to replace the original pattern to be corrected.

A method for correcting a semiconductor mask pattern includes steps as follows: A pattern to be corrected in the semiconductor mask pattern is divided into a plurality of sub-blocks that are symmetrical to and coincide with each other. Then, an optical proximity correction (OPC) step is performed on one of the plurality of sub-blocks to obtain a modified template. At least one copy template is generated according to the modified template corresponding to the other ones of the plurality of sub-blocks. The modified template and the at least one copy template are spliced to form a correcting pattern to replace the original pattern to be corrected.