Patent classifications
G03F7/70
MULTI-ELECTRON BEAM INSPECTION DEVICE AND MULTI-ELECTRON BEAM INSPECTION METHOD
A multi-electron beam inspection apparatus includes a multi-detector that includes a plurality of detection sensors each of which detects a secondary electron beam emitted due to that a target object is irradiated with a primary electron beam individually preset in multiple secondary electron beams emitted because the target object is irradiated with multiple primary electron beams, a reference image data generation circuit that generates reference image data of a position irradiated with each primary electron beam, based on design data serving as a basis of the pattern formed on the target object, a synthesis circuit that synthesizes, for each primary electron beam, the reference image data of the position irradiated with a primary electron beam concerned and portions of reference image data of positions irradiated with other primary electron beams different from the primary electron beam concerned, and a comparison circuit that compares synthetic reference image data having been synthesized, and secondary electron image data based on a value detected by the detection sensor which detects a secondary electron beam due to irradiation with the primary electron beam concerned.
METHODS AND APPARATUSES FOR DIRECTED SELF-ASSEMBLY
Provided herein is a method, including creating a first layer over a substrate, wherein the first layer is configured for directed self-assembly of a block copolymer thereover; creating a continuous second layer over the first layer by directed self-assembly of a block copolymer, wherein the second layer is also configured for directed self-assembly of a block copolymer thereover; and creating a third layer over the continuous second layer by directed self-assembly of a block copolymer. Also provided is an apparatus, comprising a continuous first layer comprising a thin film of a first, phase-separated block copolymer, wherein the first layer comprises a first chemoepitaxial template configured for directed self-assembly of a block copolymer thereon; and a second layer on the first layer, wherein the second layer comprises a thin film of a second, phase-separated block copolymer.
Pattern optical similarity determination
Aspects of the invention relate to techniques for determining pattern optical similarity in lithography. Optical kernel strength values for a first set of layout features and a second set of layout features are computed first. Based on the optical kernel strength values, optical similarity values between the first set of layout features and the second set of layout features are then determined. Subsequently, calibration weight values for the first set of layout features may be determined based on the optical similarity values, which, along with the first set of layout features, may be employed to calibrate lithography process model parameters.
Method for producing a structure
The invention relates to a method for producing a structure in a lithographic material, wherein the structure in the lithographic material is defined by means of a writing beam of an exposure device, in that a plurality of partial structures are written sequentially, wherein for writing the partial structures a write field of the exposure device is displaced and positioned sequentially and that a partial structure is written in the write field in each case, and wherein for positioning of the write field a reference structure is detected by means of an imaging measuring device. For calibration of the write field in the respectively positioned write field, before, during or after writing a partial structure, at least one reference structure element assigned to this partial structure is produced in the lithographic material with the writing beam, wherein the reference structure element after the displacement of the write field is detected by means of the imaging measuring device for writing a further partial structure.
Categorized stitching guidance for triple-patterning technology
A computer-implemented method for validating a design is disclosed. The method includes receiving, with the computer, the design, where the design is printable using a multiple-patterning process when the computer is invoked, and where the design includes a plurality of shapes and at least one conflict preventing decomposition of the design into a plurality of multiple-patterning masks. The method also includes forming a subset of the shapes, the subset including the shapes associated with the at least one conflict, categorizing each of the shapes of the subset into one of a plurality of topology types generating one or more stitch candidate solutions for each of the plurality of topology types, and decomposing the design into a plurality of masks.
Scatterometry overlay metrology targets and methods
Scatterometry overlay (SCOL) targets as well as design, production and measurement methods thereof are provided. The SCOL targets have several periodic structures at different measurement directions which share some of their structural target elements or parts thereof. An array of common elements may have symmetry directions which are parallel to the measurement directions and thus enable compacting the targets or alternatively increasing the area use efficiency of the targets. Various configurations enable high flexibility in arranging the number of layers in the target and measurement directions, and carrying out respective overlay measurements among the layers.
Method and system for triple patterning technology (TPT) violation detection and visualization
A method, system, and computer program product for triple patterning technology (TPT) violation detection and visualization within an integrated circuit design layout are disclosed. In a first aspect, the method comprises mapping a plurality of violations of the integrated circuit design layout to a graph, generating a color graph corresponding to the graph, detecting at least one TPT violation from the color graph; and visualizing the at least one TPT violation on a layout canvas. In a second aspect, the system comprises a graph generator module for mapping a plurality of violations of the integrated circuit design layout to a graph and to generate a color graph corresponding to the graph, a detector module for detecting at least one TPT violation from the color graph, and a visualizer module for visualizing the at least one TPT violation on a layout canvas.
MULTI-PASS PATTERNING USING NONREFLECTING RADIATION LITHOGRAPHY ON AN UNDERLYING GRATING
Techniques related to multi-pass patterning lithography, device structures, and devices formed using such techniques are discussed. Such techniques include exposing a resist layer disposed over a grating pattern with non-reflecting radiation to generate an enhanced exposure portion within a trench of the grating pattern and developing the resist layer to form a pattern layer having a pattern structure within the trench of the grating pattern.
Catadioptric projection objective
A projection objective for microlithography for imaging an object field onto an image field includes: a first partial objective for imaging the object field onto a first real intermediate image; a second partial objective for imaging the first intermediate image onto a second real intermediate image; a third partial objective for imaging the second intermediate image onto the image field, the third partial objective including an aperture; and a first folding mirror for deflecting radiation toward a concave mirror and a second folding mirror for deflecting the radiation from the concave mirror toward the image plane; in which the projection objective is an immersion projection objective in which during operation an immersion liquid is situated between a last lens surface and an image plane, and at least one surface of at least one lens in the second partial objective has an antireflection coating including at least six layers.
METHOD FOR IN-DIE OVERLAY CONTROL USING FEOL DUMMY FILL LAYER
Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.