According to some aspects of the present disclosure, an atomic clock and methods of forming and/or using an atomic clock are disclosed. In one embodiment, an atomic clock includes: a light source configured to illuminate a resonance vapor cell; a narrowband optical filter disposed between the light source and the resonance vapor cell and arranged such that light emitted from the light source passes through the narrowband optical filter and illuminates the resonance vapor cell. The resonance vapor cell is configured to emit a signal corresponding to a hyperfine transition frequency in response to illumination from the light source, and a filter cell is disposed between the light source and the resonance vapor cell and configured to generate optical pumping. An optical detector is configured to detect the emitted signal corresponding to the hyperfine transition frequency.

According to some aspects of the present disclosure, an atomic clock and methods of forming and/or using an atomic clock are disclosed. In one embodiment, an atomic clock includes: a light source configured to illuminate a resonance vapor cell; a narrowband optical filter disposed between the light source and the resonance vapor cell and arranged such that light emitted from the light source passes through the narrowband optical filter and illuminates the resonance vapor cell. The resonance vapor cell is configured to emit a signal corresponding to a hyperfine transition frequency in response to illumination from the light source, and a filter cell is disposed between the light source and the resonance vapor cell and configured to generate optical pumping. An optical detector is configured to detect the emitted signal corresponding to the hyperfine transition frequency.

A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.

Embodiments of the present disclosure provide a data buffering method, electronic device and computer-readable medium. The method includes receiving, at a first node of a network, time window information from a second node of the network, the time window information defining a time window when data is transmitted from the first node to the second node. The method further includes enabling a first clock circuit of the first node at least partly based on the time window information to provide a first clock signal for data transmission from the first node to the second node. Therefore, the power consumption at the first node can be effectively reduced.

Embodiments of the present disclosure provide a data buffering method, electronic device and computer-readable medium. The method includes receiving, at a first node of a network, time window information from a second node of the network, the time window information defining a time window when data is transmitted from the first node to the second node. The method further includes enabling a first clock circuit of the first node at least partly based on the time window information to provide a first clock signal for data transmission from the first node to the second node. Therefore, the power consumption at the first node can be effectively reduced.

In at least one embodiment, a method includes generating a digital time code corresponding to an input clock signal using a time-to-digital converter responsive to a reference clock signal and a time-to-digital converter calibration signal. The method includes generating the time-to-digital converter calibration signal based on the digital time code. Generating the time-to-digital converter calibration signal includes generating a digital error signal based on the digital time code and an estimated digital time code, and adapting the time-to-digital converter calibration signal based on the digital error signal.

Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

Embodiments of the present disclosure provide a data buffering method, electronic device and computer-readable medium. The method includes receiving, at a first node of a network, time window information from a second node of the network, the time window information defining a time window when data is transmitted from the first node to the second node. The method further includes enabling a first clock circuit of the first node at least partly based on the time window information to provide a first clock signal for data transmission from the first node to the second node. Therefore, the power consumption at the first node can be effectively reduced.

Embodiments of the present disclosure provide a data buffering method, electronic device and computer-readable medium. The method includes receiving, at a first node of a network, time window information from a second node of the network, the time window information defining a time window when data is transmitted from the first node to the second node. The method further includes enabling a first clock circuit of the first node at least partly based on the time window information to provide a first clock signal for data transmission from the first node to the second node. Therefore, the power consumption at the first node can be effectively reduced.