A time-to-digital converter including N stages of converting circuits, where N≧2, and N is an integer. Each stage of converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of converting circuit outputs a delayed signal of the stage of converting circuit; and the arbiter in each stage of converting circuit receives a sampling clock and the delayed signal of the stage of converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of converting circuit. Output signals of the N stages of converting circuits form a non-linear binary number, to indicate a time difference between a clock signal and a reference signal.

A time to digital converter has a counter, a first phase difference detector, a first capacitor, a second capacitor having capacitance N times a capacitance of the first capacitor, a comparator to compare a charge voltage of the first capacitor with a charge voltage of the second capacitor, a first charge controller, a first phase difference arithmetic unit, a second phase difference detector, a second charge controller, a second phase difference arithmetic unit to operate the phase difference between the first signal and the second signal, and a third phase difference arithmetic unit to detect a fractional phase difference between the first signal and the second signal. The first phase difference arithmetic unit operates the phase difference between the first signal and the second signal, based on a reference phase, when the counter suspends a measurement operation.

A semiconductor body includes a driver for driving a light source, at least two detectors each including an avalanche diode, a time-to-digital converter arrangement coupled to outputs of the at least two detectors, a memory that is coupled to the time-to-digital converter arrangement and is configured to store at least one histogram, and an evaluation unit coupled to the driver and to the memory.

A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.

Various embodiments of the present technology may comprise methods and apparatus for a multi-cycle time-based ADC configured to convert an analog signal to a digital value. Methods and apparatus a multi-cycle time-based ADC according to various aspects of the present invention may comprise a plurality of VTCs configured to perform multiple voltage-to-time conversions out-of-phase from each other. The integration times for each VTC may be summed to provide a total integration time, which may then be converted to the digital value.

A method for digitalizing a scintillation pulse may include: S1, acquiring a pulse database outputted by a detector irradiated by rays of different energy; S2, sampling and 5 quantizing each of pulses in the pulse database obtained in S1 to acquire complete energy information comprised in the pulse; S3, undersampling and quantizing each of the pulses in the pulse database obtained in step S1, and estimating or fitting energy information by using pulse prior information; S4, with the energy information obtained in S2 as a standard, determining a mapping relationship between 10 the energy information obtained by a prior information-based undersampling pulse energy acquisition method and the energy information obtained by the method of S2; and S5 correcting the energy information obtained by the prior information-based undersampling pulse energy acquisition method by using the energy mapping relationship obtained in S4.

A method for compensating signal nonlinearities includes generating a local oscillator (LO) signal and performing phase modulation of the LO signal to generate a phase-modulated LO signal. The phase modulation is based on applying at least one digital-to-time converter (DTC) code of a plurality of DTC codes to a rising edge signal portion and a falling edge signal portion associated with the LO signal. Nonlinearities associated with the rising edge signal portion and the falling edge signal portion are determined. The at least one DTC code is adjusted based on the nonlinearities.

A wireless communication device, including a radiofrequency frontend, configured to wirelessly receive a radiofrequency signal; perform one or more analog baseband operations on the received radiofrequency signal, according to a radio access technology; and output an analog signal representing an output of the analog baseband operations on the received radiofrequency signal; an error corrector, configured to perform an error correction operation on the analog signal; and output an error corrected signal in analog domain; and the analog-digital converter, configured to convert the error corrected signal to digital domain.

A two-stage successive-approximation-register (SAR) analog-to-digital converter (ADC) comprising is described. The SAR ADC includes a first stage comprising a SAR ADC; a voltage-to-time interface that translates a voltage-domain residue from the SAR ADC to a time-domain residue; and a second stage comprising a time-to-digital converter (TDC) that resolves multiple bits from the time-domain residue.

A Time to Digital Converter (TDC) arrangement includes a first delay circuit configured to receive a signal with N phases; a set of phase detectors configured to compare each phase of the signal with a reference signal; a logic circuit configured to receive output signals from the set of phase detectors and detect which phase signal that is the closest signal leading or lagging the reference signal; a first multiplexer configured to receive outputs from the first delay circuit and the logic circuit; a second delay circuit configured to delay the reference signal; a TDC configured to receive output signals from the first multiplexer and the second delay circuit; an adder configured to sum outputs from the logic circuit and the TDC and generate an output signal of the TDC arrangement.