A time-to-digital converter utilizes both coarse and fine quantizers and addresses mismatch by using redundant bits in the coarse time representation and the fine time representation. The redundant bits are compared and if the redundant bits are the same, no mismatch correction is required but if the redundant bits are different a correction is applied to correct the redundant portion of the coarse time information. The redundant portion includes the most significant bit generated by the fine quantizer and the least significant bit of the coarse quantizer. The correction adds to or subtracts from the redundant information.

An analog-to-digital converter (ADC) circuit is configured to receive an analog input signal and convert the analog input signal to a digital output signal. The ADC circuit includes a first circuit that is configured to convert the analog input signal into a first digital signal that includes a first subset of bits of the digital output signal and further provide a residue signal based on the first digital signal; and a second circuit, coupled to the first circuit, and is configured to determine a discharging time duration by simultaneously amplifying and discharging the residue signal.

A time-to-digital converter includes a self-calibrating, n-stage chain of a number n of gate delay elements connected in parallel and series between a clock signal line for supplying a clock signal and a stop signal line for supplying a stop signal; and a charge-pump and phase-detector unit for the feedback control of the gate delay elements, having a first input as a controlled-variable input, a second input as a reference-variable input, and an output as a correcting-variable output. The clock signal line is connected to the first input of the charge-pump and phase-detector unit, a push-pull line for supplying a push-pull signal is connected to the second input, and, for feedback, the gate delay elements are connected to the output of the charge-pump and phase-detector unit.

A system includes a digital-to-time converter (DTC) to generate output signals with phase offsets set by a plurality of DTC input values and a time-to-digital converter (TDC) operatively coupled to the DTC, wherein the TDC has a lower resolution than the DTC. The system also includes a processing component operatively coupled to the DTC and the TDC. The processing device, for each of a plurality of TDC thresholds, determines a DTC input value corresponding to a respective TDC threshold. The processing device may then generate a calibration function based on the determined DTC input values and corresponding TDC thresholds.

Various embodiments include a time to digital converter device comprising: a medium resolution delay unit including a plurality of buffers, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals wherein the delay between the plurality of delayed data clock signal is a medium resolution delay value; a fine resolution delay unit including a plurality of cores configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit, wherein the plurality of cores includes: a first bank of delays configured to receive one of the plurality of the delayed data clock signals, a second bank of delays configured to receive the reference clock signal, and; and a fast flip flop connected to the outputs of the first bank of delays and the second bank of delays, wherein the output of the fast flip flop is used to check the phase alignment.

A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.

A time measurement device for calculating a time from an input of a first trigger signal to an input of a second trigger signal as a measured time includes a start gate configured to generate a start signal, a stop gate configured to generate a stop signal, a TDC circuit configured to generate a digital code corresponding to the time from an input of a start signal to an input of a stop signal, a delay circuit configured to delay an input of at least one of the start signal and the stop signal to the TDC circuit by a predetermined delay time, and a control unit configured to calculate a measured time on the basis of a plurality of digital codes generated by the TDC circuit, wherein the time delay unit selects at least two delay times.

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Provided is a data transmitter including a signal interval determination unit configured to receive a data input signal corresponding to data to be transmitted, determine time intervals between a synchronization signal and a plurality of data signals according to the data input signal, and output interval signals corresponding to the intervals; a trigger generation unit configured to trigger according to an output signal from the signal interval determination unit; and a signal generation unit configured to receive the trigger to generate the synchronization signal and the data signals.

A method for calibrating a phase nonlinearity of a digital-to-time converter is provided. The method includes generating, based on a control word, a reference signal using a phase-locked loop. A frequency of the reference signal is equal to a frequency of an output signal of the digital-to-time converter. Further, the method includes measuring a temporal order of a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level. The method additionally includes adjusting a first entry of a look-up table based on the measured temporal order.