A time measurement device measures a time interval between input timings of first and second pulsed target signals. The device includes: a processor; a number-of-periods detector that detects, by using a clock signal with a predetermined clock frequency and a predetermined clock period, the time interval in units of the clock period; and a phase detection unit including a band-pass filter. The band-pass filter receives at least one of the first and second target signals as a filtering target signal and extracts a signal component of the clock frequency from the filtering target signal. The phase detection unit detects a phase difference between the extracted signal and the clock signal. The processor derives, by using a result detected by the number-of-periods detector and the detected phase difference, the time interval at a resolution finer than the clock period.

A physical quantity measurement apparatus includes a first resonator, a second oscillator, and an integrated circuit device. The integrated circuit device includes a first oscillation circuit that causes the first resonator to oscillate, and thus generate a first clock signal having a first clock frequency, a second oscillation circuit that causes the second oscillator to oscillate, and thus generate a second clock signal having a second clock frequency which is different from the first clock frequency, and a measurement unit that is provided with a time-to-digital conversion circuit which converts time into a digital value by using the first clock signal and the second clock signal.

A physical quantity measurement apparatus includes a first resonator, a second oscillator, and an integrated circuit device. The integrated circuit device includes a first oscillation circuit that causes the first resonator to oscillate, and thus generate a first clock signal having a first clock frequency, a second oscillation circuit that causes the second oscillator to oscillate, and thus generate a second clock signal having a second clock frequency which is different from the first clock frequency, and a measurement unit that is provided with a time-to-digital conversion circuit which converts time into a digital value by using the first clock signal and the second clock signal.

A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit includes a first falling edge delay circuit that delays a falling edge based on a first input signal, a first rising edge delay circuit that delays a rising edge based on a second input signal, and a first output circuit. A second delay unit includes a second falling edge delay circuit that delays a falling edge based on the second input signal, a second rising edge delay circuit that delays a rising edge based on the first input signal, and a second output circuit.

A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit includes a first falling edge delay circuit that delays a falling edge based on a first input signal, a first rising edge delay circuit that delays a rising edge based on a second input signal, and a first output circuit. A second delay unit includes a second falling edge delay circuit that delays a falling edge based on the second input signal, a second rising edge delay circuit that delays a rising edge based on the first input signal, and a second output circuit.

A controller, which is installed on a power supply device complying with the USB (Universal Serial Bus)-PD (power delivery) specification and controls a power supply circuit for supplying a bus voltage to a power receiving device via a bus line is disclosed. The controller includes an interface circuit, which communicates with the power supply device via the bus line; a processor, which transmits and receives messages to and from the power receiving device by using the interface circuit, determines a voltage level of the bus voltage, and sets the determined voltage level to the power supply circuit; and a watchdog timer, which is cleared whenever the processor executes a ping-related command for transmission or reception of ping messages to or from the power receiving device, wherein an overflow period of the watchdog timer is set to be longer than a period for the ping messages.

A reconfigurable and timely accurate method of generating, with a low latency, an output signal in response to multiple input signals, wherein said input signals occur at independent times, and wherein the occurrence of several input signals according to predetermined pattern is interpreted as a Super Event and wherein a detected Super Event triggers the production of a specific output signal heralding this Super Event, characterized in that said method comprises a first step of time acquisition of the occurrence of said input signals, a second step of adaptation of the acquisition data flow to the clock of the reconfigurable processing unit, a third step of determining the occurrence of a Super Event by comparing the events pattern to the super event definition, a fourth step identifying the Super Event and generating at least one event/signal corresponding to at least one trigger signal, a fifth step of adaptation of the generation data flow to the asynchronous generation device, a sixth step of applying a predefined delay for the issue of the at least one trigger signal, and an seventh step of outputting at least one output signal representing a trigger signal and sending it to a downstream unit.

A system and a memory device including a driver circuit, to perform first operations including driving a resistor-capacitor (RC) sensor circuit of an electronic device to a drive voltage using a representative copy of a current that drives an electronic circuit line of the electronic device. The system and memory device including the RC sensor circuit, coupled to the driver circuit, to perform second operations including determining a first sample voltage by sampling a first representative voltage generated at the RC sensor circuit, and determining a second sample voltage by sampling a second representative voltage generated at the RC sensor circuit. The ratio of the first sample voltage and the second sample voltage is indicative of an RC time constant of the electronic circuit line.

A time to digital converter (TDC) with high resolution is provided. The TDC includes a counter, a reference value generator and a comparator. The counter samples an input signal according to a clock signal to calculate a pulse width of the input signal. The reference value generator samples a ruler signal according to the clock signal to generate a reference value. Herein, a frequency of the clock signal is greater than a frequency of the ruler signal, and the frequency of the ruler signal is greater than a frequency of the input signal. The comparator is coupled to the counter and the reference value generator, and compares the pulse width of the input signal and the reference value to generate a count result.

A time to digital converter (TDC) with high resolution is provided. The TDC includes a counter, a reference value generator and a comparator. The counter samples an input signal according to a clock signal to calculate a pulse width of the input signal. The reference value generator samples a ruler signal according to the clock signal to generate a reference value. Herein, a frequency of the clock signal is greater than a frequency of the ruler signal, and the frequency of the ruler signal is greater than a frequency of the input signal. The comparator is coupled to the counter and the reference value generator, and compares the pulse width of the input signal and the reference value to generate a count result.