An area efficient amplifier that amplifies a continuous-time continuous-amplitude signal and converts it to a discrete-time discrete-amplitude signal. The amplifier includes a first oscillator having an input and a plurality of N outputs and a second oscillator having an input and N outputs. The amplifier includes N phase detectors, each phase detector has a first input, a second input, a first output, and a second output, where each first input of each phase detector is coupled to respective one of the N outputs of the first oscillator, where each second input of each phase detector is coupled to respective one of the N outputs of the second oscillator. The amplifier includes N quantizers, each quantizer has a data input, a clock input, and an output, where each data input of each quantizer is coupled to respective one first output or one second output of the N phase detectors.

In accordance with some embodiments, polarity-coincidence, adaptive time-delay estimation (PCC-ATDE), mixed-signal techniques are provided. In some embodiments, these techniques use 1-bit quantized signals and negative-feedback architectures to directly determine a time-delay between signals at analog inputs and convert the time-delay to a digital number.

In accordance with some embodiments, polarity-coincidence, adaptive time-delay estimation (PCC-ATDE), mixed-signal techniques are provided. In some embodiments, these techniques use 1-bit quantized signals and negative-feedback architectures to directly determine a time-delay between signals at analog inputs and convert the time-delay to a digital number.

Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency.

An area efficient amplifier that amplifies a continuous-time continuous-amplitude signal and converts it to a discrete-time discrete-amplitude signal. The amplifier includes a first oscillator having an input and a plurality of N outputs and a second oscillator having an input and N outputs. The amplifier includes N phase detectors, each phase detector has a first input, a second input, a first output, and a second output, where each first input of each phase detector is coupled to respective one of the N outputs of the first oscillator, where each second input of each phase detector is coupled to respective one of the N outputs of the second oscillator. The amplifier includes N quantizers, each quantizer has a data input, a clock input, and an output, where each data input of each quantizer is coupled to respective one first output or one second output of the N phase detectors.

An area efficient amplifier that amplifies a continuous-time continuous-amplitude signal and converts it to a discrete-time discrete-amplitude signal. The amplifier includes a first oscillator having an input and a plurality of N outputs and a second oscillator having an input and N outputs. The amplifier includes N phase detectors, each phase detector has a first input, a second input, a first output, and a second output, where each first input of each phase detector is coupled to respective one of the N outputs of the first oscillator, where each second input of each phase detector is coupled to respective one of the N outputs of the second oscillator. The amplifier includes N quantizers, each quantizer has a data input, a clock input, and an output, where each data input of each quantizer is coupled to respective one first output or one second output of the N phase detectors.

A delay time detection circuit includes below configurations. A clock generation unit generates a sub scale clock signal, based on a system clock signal. A count unit generates a count signal while sequentially and repeatedly incrementing a count number, based on the sub scale clock signal. A sub scale signal generation unit receives the count signal, and generates sub scale signals, equal in number to the count number, that each have, at a rate of once in the count number, a rectangular wave for a duration being associated with a second period and that are shifted in timing relative to one another according to the second period. A delay time calculation unit receives the input clock signal, and calculates a delay time within a range of the first period of the input clock signal with respect to the system clock signal, based on one of the sub scale signals.

A delay time detection circuit includes below configurations. A clock generation unit generates a sub scale clock signal, based on a system clock signal. A count unit generates a count signal while sequentially and repeatedly incrementing a count number, based on the sub scale clock signal. A sub scale signal generation unit receives the count signal, and generates sub scale signals, equal in number to the count number, that each have, at a rate of once in the count number, a rectangular wave for a duration being associated with a second period and that are shifted in timing relative to one another according to the second period. A delay time calculation unit receives the input clock signal, and calculates a delay time within a range of the first period of the input clock signal with respect to the system clock signal, based on one of the sub scale signals.

A time measurement device measures a time interval between input timings of first and second pulsed target signals. The device includes: a processor; a number-of-periods detector that detects, by using a clock signal with a predetermined clock frequency and a predetermined clock period, the time interval in units of the clock period; and a phase detection unit including a band-pass filter. The band-pass filter receives at least one of the first and second target signals as a filtering target signal and extracts a signal component of the clock frequency from the filtering target signal. The phase detection unit detects a phase difference between the extracted signal and the clock signal. The processor derives, by using a result detected by the number-of-periods detector and the detected phase difference, the time interval at a resolution finer than the clock period.

A time measurement device measures a time interval between input timings of first and second pulsed target signals. The device includes: a processor; a number-of-periods detector that detects, by using a clock signal with a predetermined clock frequency and a predetermined clock period, the time interval in units of the clock period; and a phase detection unit including a band-pass filter. The band-pass filter receives at least one of the first and second target signals as a filtering target signal and extracts a signal component of the clock frequency from the filtering target signal. The phase detection unit detects a phase difference between the extracted signal and the clock signal. The processor derives, by using a result detected by the number-of-periods detector and the detected phase difference, the time interval at a resolution finer than the clock period.