Systems and methods for detecting the failure of a precision time source using an independent time source are disclosed. Additionally, detecting the failure of a GNSS based precision time source based on a calculated location of a GNSS receiver is disclosed. Moreover, the system may be further configured to distribute a time derived from the precision time source as a precision time reference to time dependent devices. In the event of a failure of the precision time source, the system may be configured to distribute a time derived from a second precision time source as the precision time signal during a holdover period.

A time-to-voltage converter (TVC) that includes a 555 timer integrated circuit (IC), and a charging circuit including a constant current source and a capacitor connected in series. The capacitor can be connected to a discharge pin of the 555 timer IC. The TVC can further include a trigger circuit and a reset circuit to receive a start signal and a stop signal, respectively, from an input line, and accordingly generate a trigger signal or a reset signal to trigger or reset the 555 timer IC. A switch can be configured to, under control of an output signal of the 555 timer IC, connect the input line with the reset circuit. A voltage across the capacitor when the 555 timer IC is reset indicates a time interval corresponding to the start and stop signals.

A time-to-voltage converter (TVC) that includes a 555 timer integrated circuit (IC), and a charging circuit including a constant current source and a capacitor connected in series. The capacitor can be connected to a discharge pin of the 555 timer IC. The TVC can further include a trigger circuit and a reset circuit to receive a start signal and a stop signal, respectively, from an input line, and accordingly generate a trigger signal or a reset signal to trigger or reset the 555 timer IC. A switch can be configured to, under control of an output signal of the 555 timer IC, connect the input line with the reset circuit. A voltage across the capacitor when the 555 timer IC is reset indicates a time interval corresponding to the start and stop signals.

An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.

An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.

A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.

A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.

Disclosed is a time-to-digital converter (TDC)-based device comprising a crossbar array for generating a current, a current-controlled delay line 104 for converting the current received from the crossbar array into a time pulse, and a TDC circuit 106 for measuring and converting the time pulse into digital output.

Disclosed is a time-to-digital converter (TDC)-based device comprising a crossbar array for generating a current, a current-controlled delay line 104 for converting the current received from the crossbar array into a time pulse, and a TDC circuit 106 for measuring and converting the time pulse into digital output.

A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.