An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.

The time base includes an oscillator generating a periodic signal, a frequency divider circuit formed by a division chain defining several division stages and a circuit for adjusting the divided frequency by inhibiting, in each inhibition period of a plurality of successive inhibition periods, an integer number of clocking pulses at the input of a given stage of the division chain. The time base is arranged to produce, in each inhibition period, a first real number corresponding to the real number of clocking pulses that must be removed to be precise and the adjustment circuit is arranged to calculate, in each inhibition period, a second real number equal to the addition of the first real number and the fractional part of the second real number obtained in the preceding inhibition period, the integer part of this second real number defining the number of clocking pulses to be inhibited in each inhibition period.

The invention provides a timing apparatus that can generate timing information regarding a plurality of regions without performing a complex calculation that uses software and without causing a significant increase in electric current consumption. The timing apparatus includes: a lower counter that generates a count value that indicates a time in seconds; a first group of upper counters that generates a first group of count values that indicate a time in minutes, hours, days, months and years by performing a count operation in synchronization with the count operation performed by the lower counter; and a second group of upper counters that generates a second group of count values that indicate a time in minutes, hours, days, months and years by performing a count operation in synchronization with the count operation performed by the lower counter.

An integrated circuit comprising, a resonator, a first clock circuit for generating a first clock signal having a first frequency in response to the resonator, a second clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is determined by the programmable frequency divider and a clock mode control circuit coupled to the first clock circuit and the second clock circuit, the clock mode control circuit for gradually switching the resonator between the first oscillator circuit and the second oscillator circuit of the integrated circuit, using a shift register based state machine and utilizing the inertia of the resonator to smoothly transition between the two oscillators, to provide a dual mode clock output signal.

A real-time clock device includes an input terminal to which a reference pulse signal of a time is input, an oscillation circuit that outputs an oscillation clock signal, a clock count circuit that generates information on an internal time based on the oscillation clock signal, and a processing circuit that performs, in a case in which it is determined that a time lag occurs at the internal time when the reference pulse signal is input, frequency correction of the oscillation clock signal based on a time lag amount and a time interval of the time lag, and time correction of the internal time.

A real-time clock device includes an input terminal to which a reference pulse signal of a time is input, an oscillation circuit that outputs an oscillation clock signal, a clock count circuit that generates information on an internal time based on the oscillation clock signal, and a processing circuit that performs, in a case in which it is determined that a time lag occurs at the internal time when the reference pulse signal is input, frequency correction of the oscillation clock signal based on a time lag amount and a time interval of the time lag, and time correction of the internal time.