A clock source includes a comparator having a positive comparator input, a negative comparator input, a proportional to absolute temperature (PTAT) PMOS bias input, a PTAT NMOS bias input, and a comparator output, a resonator element, series and feedback resistors and other passive components coupled between the comparator output and the negative comparator input to generate a signal with approximately constant gain and frequency at the comparator output, and a PTAT bias circuit coupled to the comparator's PTAT PMOS and NMOS bias inputs, and configured to drive the PTAT PMOS bias input and the PTAT NMOS bias input to maintain approximately constant gain and frequency over the operating temperature range of the clock source.

A variety of active units that sense environmental variables and take various actions are described. In one embodiment, an active unit includes at least one sensor to detect a change in an environmental variable and generate a sensor signal and an action module configured to influence the environmental. The active unit may also include a communication module and a processor module configured to accept the sensor signal and determine if the environmental variable exceeds a threshold and to instruct the action module not to take action to influence the environmental variable, and instruct the communication module to transmit a signal to other active units that the environmental variable has exceeded the threshold.

A variety of active units that sense environmental variables and take various actions are described. In one embodiment, an active unit includes at least one sensor to detect a change in an environmental variable and generate a sensor signal and an action module configured to influence the environmental. The active unit may also include a communication module and a processor module configured to accept the sensor signal and determine if the environmental variable exceeds a threshold and to instruct the action module not to take action to influence the environmental variable, and instruct the communication module to transmit a signal to other active units that the environmental variable has exceeded the threshold.

A power gating circuit includes inverters and a voltage divider sub-circuit, a latch comparator, and a gated switch sub-circuit connected to an external power supply circuit of 5V, respectively. The voltage divider sub-circuit is configured to divide a voltage of 5V and output a first voltage and a second voltage to the latch comparator and the gated switch sub-circuit, both voltage values of the first voltage and the second voltage are smaller than a withstand voltage value of a field effect transistor, and the voltage value of the first voltage is greater than that of the second voltage; the latch comparator is configured to compare two signals output by the inverters and latch a comparison result; and the gated switch sub-circuit is further connected with the latch comparator to control an output voltage, thereby improving the stability of the circuit, and extending the using life of the entire circuit.

A power gating circuit includes inverters and a voltage divider sub-circuit, a latch comparator, and a gated switch sub-circuit connected to an external power supply circuit of 5V, respectively. The voltage divider sub-circuit is configured to divide a voltage of 5V and output a first voltage and a second voltage to the latch comparator and the gated switch sub-circuit, both voltage values of the first voltage and the second voltage are smaller than a withstand voltage value of a field effect transistor, and the voltage value of the first voltage is greater than that of the second voltage; the latch comparator is configured to compare two signals output by the inverters and latch a comparison result; and the gated switch sub-circuit is further connected with the latch comparator to control an output voltage, thereby improving the stability of the circuit, and extending the using life of the entire circuit.

A gallium nitride (GaN) transistor-based regulated voltage source has a reference voltage input coupled to a reference voltage. The regulated voltage source also includes an input port and an output port. The regulated voltage source includes a GaN transistor-based voltage regulation path coupling the input port and the output port with at least a GaN regulation transistor with a threshold voltage and that is formed on a substrate. The regulated voltage source also includes a GaN transistor-based voltage compensator having an intermediate GaN transistor that is also formed on the substrate. The GaN transistor-based voltage compensator couples a gate of the GaN regulation transistor to the reference voltage input and introduces a voltage drop between the gate of the GaN regulation transistor and the reference voltage input to compensate for the threshold voltage of the GaN regulation transistor.

A circuit for controlling an input current, the circuit includes a first input port configured to receive the input current. A current detector detects an input current value of the input current and generates a control signal indicative of the input current value. A first output port outputs an output current to a load. A second output port receives the output current from the load. A control circuit provides a low-impedance path in parallel with the load in response to the control signal indicating the input current value is below a threshold value.

A circuit for controlling an input current, the circuit includes a first input port configured to receive the input current. A current detector detects an input current value of the input current and generates a control signal indicative of the input current value. A first output port outputs an output current to a load. A second output port receives the output current from the load. A control circuit provides a low-impedance path in parallel with the load in response to the control signal indicating the input current value is below a threshold value.

A memory device comprising multiple memory planes is disclosed. The memory device further comprises a first pump set coupled with the multiple memory planes, and configured to supply a first output voltage to multiple linear regulators during a steady phase, and a second pump set coupled with the multiple memory planes, and configured to supply a second output voltage to the multiple linear regulators during a ramping phase. The multiple linear regulators can includes a first linear regulator set configured to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first group of word lines of the plurality of memory planes, and a second linear regulator set configured to regulate the first output voltage or the second output voltage to generate a second voltage bias for a second group of word lines of the plurality of memory planes.

A memory device comprising multiple memory planes is disclosed. The memory device further comprises a first pump set coupled with the multiple memory planes, and configured to supply a first output voltage to multiple linear regulators during a steady phase, and a second pump set coupled with the multiple memory planes, and configured to supply a second output voltage to the multiple linear regulators during a ramping phase. The multiple linear regulators can includes a first linear regulator set configured to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first group of word lines of the plurality of memory planes, and a second linear regulator set configured to regulate the first output voltage or the second output voltage to generate a second voltage bias for a second group of word lines of the plurality of memory planes.