A power converter with an isolated topology may include a power transistor, a sense transistor, and a read-out circuit. The sense transistor may be arranged in a current mirror configuration with the power transistor such that the gate terminal of the sense transistor is coupled to the gate terminal of the power transistor and the first drain/source terminal of the sense transistor is coupled to the first drain/source terminal of the power transistor. The read-out circuit may be coupled to the second drain/source terminal of the power transistor and the second drain source/terminal of the sense transistor. The read-out circuit may be arranged to cause a voltage at the second drain/source terminal of the sense transistor to be substantially the same as a voltage at the second drain/source terminal of the power transistor.

Methods and apparatus relating to dynamic voltage regulator sensing and/or reference voltage setting techniques for multiple gated loads are described. In an embodiment, voltage regulator logic is coupled to one or more loads. Each of the one or more loads is in a separate power domain. The voltage regulator logic controls a sensed voltage from the one or more loads in response to a power gate control signal. Other embodiments are also disclosed and claimed.

Methods and apparatus relating to dynamic voltage regulator sensing and/or reference voltage setting techniques for multiple gated loads are described. In an embodiment, voltage regulator logic is coupled to one or more loads. Each of the one or more loads is in a separate power domain. The voltage regulator logic controls a sensed voltage from the one or more loads in response to a power gate control signal. Other embodiments are also disclosed and claimed.

A cascaded configuration of regulator circuits can be co-integrated within a commonly-shared integrated circuit package (such as an integrated electronic module). Such co-integration can include placing a switched-mode regulator circuit in close proximity to a linear regulator circuit. Magnetic field coupling between the regulator circuits is generally a non-linear function of a separation between the circuits. The switched-mode regulator circuit can generate noise that may adversely impact the linear regulator output. Magnetic coupling between the regulator circuits within the module package can be suppressed or eliminated using a magnetic barrier. The barrier can be magnetically permeable and electrically non-conductive.

An electronic device disclosed herein includes mechanisms for modeling and dynamically controlling transmission power of an electronic device. The electronic device determines a back-off function defining at least one transmission power adjustment that is effective to adjust a predicted average energy emanating from an electronic device over the future time interval to satisfy a power condition. Power of the electronic device is adjusted according to the back-off function responsive to satisfaction of a proximity condition.

An electronic device disclosed herein includes mechanisms for modeling and dynamically controlling transmission power of an electronic device. The electronic device determines a back-off function defining at least one transmission power adjustment that is effective to adjust a predicted average energy emanating from an electronic device over the future time interval to satisfy a power condition. Power of the electronic device is adjusted according to the back-off function responsive to satisfaction of a proximity condition.

In an embodiment, an electronic device includes a first amplifier having a non-inverting input configured to receive a reference voltage and an inverting input coupled to a first output node, where the first amplifier is configured to produce a first output voltage at the first output node. The electronic device also includes a second amplifier having a non-inverting input coupled to a ground reference level, and an inverting input coupled to the first output node via a first resistor and to a second output node via a second resistor, where the second amplifier is configured to produce a second output voltage at the second output node.

A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

A current mirror circuit provides a current to drive a load. A noise cancelling circuit is provided to keep the load current constant in spite of variations in the supply voltage. The noise cancelling circuit includes an auxiliary current path which branches from the load current path. The length-to-width ratios of transistors of the circuit are selected to provide the desired noise cancellation while maintaining device stability.