Patent classifications
G05F3/02
Noise canceling current mirror circuit for improved PSR
A current mirror circuit provides a current to drive a load. A noise cancelling circuit is provided to keep the load current constant in spite of variations in the supply voltage. The noise cancelling circuit includes an auxiliary current path which branches from the load current path. The length-to-width ratios of transistors of the circuit are selected to provide the desired noise cancellation while maintaining device stability.
Control circuit and control system
One embodiment of the present application discloses a control circuit comprising a driving circuit which comprises a voltage adjusting circuit, a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. A control system comprising the control circuit is also disclosed.
Control circuit and control system
One embodiment of the present application discloses a control circuit comprising a driving circuit which comprises a voltage adjusting circuit, a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. A control system comprising the control circuit is also disclosed.
Wetting current sequencing for low current interface
A process for automated contact wetting in a sensor circuit includes generating a first current through a contact by sequencing a first circuit on, the first current exceeding a wetting threshold of the contact, and reducing current through the contact to a second current by sequencing a second circuit on, the second current being below the wetting threshold.
Wetting current sequencing for low current interface
A process for automated contact wetting in a sensor circuit includes generating a first current through a contact by sequencing a first circuit on, the first current exceeding a wetting threshold of the contact, and reducing current through the contact to a second current by sequencing a second circuit on, the second current being below the wetting threshold.
ELECTRONIC DEVICE ATTACHABLE EXTERNAL STORAGE MEDIA
An electronic device includes a tray comprising a first external storage medium and a second external storage medium, a connection circuit comprising a plurality of first contacts configured to be electrically connected to the first external storage medium and a plurality of second contacts configured to be electrically connected to the second external storage medium when the tray is attached to the electronic device, a power management circuit configured to be electrically connected to at least one part of the connection circuit, a detector configured to detect that the tray is moved to be attached to or detached from the electronic device, and a processor electrically connected to the detector and the power management circuit, wherein the processor is configured to adjust the power management circuit to control power provided to at least one part of the plurality of first contacts or second contacts when the tray is moved to be attached to or detached from the electronic device.
ELECTRONIC DEVICE ATTACHABLE EXTERNAL STORAGE MEDIA
An electronic device includes a tray comprising a first external storage medium and a second external storage medium, a connection circuit comprising a plurality of first contacts configured to be electrically connected to the first external storage medium and a plurality of second contacts configured to be electrically connected to the second external storage medium when the tray is attached to the electronic device, a power management circuit configured to be electrically connected to at least one part of the connection circuit, a detector configured to detect that the tray is moved to be attached to or detached from the electronic device, and a processor electrically connected to the detector and the power management circuit, wherein the processor is configured to adjust the power management circuit to control power provided to at least one part of the plurality of first contacts or second contacts when the tray is moved to be attached to or detached from the electronic device.
Dynamic biasing for regulator circuits
The disclosed invention provides apparatus and methods for dynamic biasing in electronic systems and circuits. The apparatus and methods disclosed provide non-linear biasing responsive to monitored load conditions.
Curvature-corrected bandgap reference
A curvature-corrected bandgap reference comprising a first BJT device operating at a first current density that is substantially proportional to absolute temperature, the first BJT device having a first base-emitter voltage and a first base terminal and a second BJT device operating at a second current density that is substantially independent of temperature, the second BJT device having a second base-emitter voltage and a second base terminal. The first and second base terminals operate at a reference voltage. The reference voltage comprises a linear combination of the first and second base-emitter voltages and is thereby made substantially independent of temperature and curvature-corrected. The linear combination is provided by summing the first base-emitter voltage, a proportional to absolute temperature (PTAT) voltage proportional to a first current density, and a curvature-correction voltage proportional to a difference between the first and second base-emitter voltages.
Curvature-corrected bandgap reference
A curvature-corrected bandgap reference comprising a first BJT device operating at a first current density that is substantially proportional to absolute temperature, the first BJT device having a first base-emitter voltage and a first base terminal and a second BJT device operating at a second current density that is substantially independent of temperature, the second BJT device having a second base-emitter voltage and a second base terminal. The first and second base terminals operate at a reference voltage. The reference voltage comprises a linear combination of the first and second base-emitter voltages and is thereby made substantially independent of temperature and curvature-corrected. The linear combination is provided by summing the first base-emitter voltage, a proportional to absolute temperature (PTAT) voltage proportional to a first current density, and a curvature-correction voltage proportional to a difference between the first and second base-emitter voltages.