A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.

Digital data processing circuitry is described that uses combinatorial logic hardware and sequential logic hardware to process one or more inputs. For each input a periodic sequence is generated that is based at least in part on a value of the input and a weight value. A match is determined at an event time when the periodic sequence(s) matches a corresponding arbitrary reference pattern. The digital data processing circuitry may be implemented as an integrated circuit as part of an interconnected network of devices that may be trained and subsequently used for recognition or other complex data processing tasks.

Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.

A measurement system for determining a phase and amplitude influence of a device under test, comprising a measurement instrument having a signal generator, a local oscillator, a first mixer and an analysis unit is disclosed. The signal generator is configured to generate a source signal with a predetermined source frequency and a source phase, and to forward the source signal to the device under test, wherein the source signal is altered by the device under test in at least one of amplitude and phase, such that a measurement signal is generated and forwarded to the first mixer. The local oscillator is configured to generate a local oscillator signal with a predetermined local oscillator frequency and a local oscillator phase, and to forward the local oscillator signal to the first mixer. The first mixer is configured to mix the measurement signal and the local oscillator signal, thereby generating a first mixer signal. The analysis unit is located downstream of the first mixer and is configured to analyze the first mixer signal or a processed version of the first mixer signal. The measurement instrument is configured to perform at least two measurements of the phase and amplitude influence of the device under test by analyzing the first mixer signal or the processed version of the first mixer signal, wherein at least one of the source phase and the local oscillator phase is altered between the at least two measurements.

A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency f.sub.CLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2.sup.n)×2π radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate f.sub.CLK, to produce a full-speed serialized digital output having 2.sup.n/M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency f.sub.OUT=(M/2.sup.n)×f.sub.CLK.

A system may include a signal generator configured to generate a raw waveform signal and a modeling subsystem configured to implement a discrete time model of an electromagnetic load that emulates a virtual electromagnetic load and further configured to modify the raw waveform signal to generate a waveform signal for driving the electromagnetic load by modifying the virtual electromagnetic load to have a desired characteristic, applying the discrete time model to the raw waveform signal to generate the waveform signal for driving the electromagnetic load, and applying the waveform signal to the electromagnetic load.

Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

An equipment rack that includes a modular compute chassis, a modular processing unit located in the modular compute chassis and where the modular processing unit is configured to remove from the front of the modular compute chassis in a frontward direction, relative to the front side of the modular compute chassis, and an air mover unit located in the modular processing unit and where the air mover unit is configured to remove from a rear side of the modular processing unit in a rearward direction, relative to the front side of modular compute chassis.

An equipment rack that includes a modular compute chassis, a modular processing unit located in the modular compute chassis and where the modular processing unit is configured to remove from the front of the modular compute chassis in a frontward direction, relative to the front side of the modular compute chassis, and an air mover unit located in the modular processing unit and where the air mover unit is configured to remove from a rear side of the modular processing unit in a rearward direction, relative to the front side of modular compute chassis.