A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

Processor-based systems employing local dynamic power management based on controlling performance and operating power consumption, and related methods. The processor-based system is configured to locally manage its power consumption by dynamically adjusting operating frequency and/or operating voltage of power supplied to the processor-based system. The processor-based system includes a power control circuit that is aware of the overall power budget for the processor-based system. The control processor in the processor-based system can dynamically increase the voltage level of the power supplied to the processor-based system and/or the operating frequency if the consumed power is lower than the power budget. The power control circuit can also dynamically decrease the operating frequency and/or the voltage level of the power supplied to the processor-based system if the consumed power is higher than the power budget.

Processor-based systems employing local dynamic power management based on controlling performance and operating power consumption, and related methods. The processor-based system is configured to locally manage its power consumption by dynamically adjusting operating frequency and/or operating voltage of power supplied to the processor-based system. The processor-based system includes a power control circuit that is aware of the overall power budget for the processor-based system. The control processor in the processor-based system can dynamically increase the voltage level of the power supplied to the processor-based system and/or the operating frequency if the consumed power is lower than the power budget. The power control circuit can also dynamically decrease the operating frequency and/or the voltage level of the power supplied to the processor-based system if the consumed power is higher than the power budget.

In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

A data backup method of a storage device which includes a storage controller, a buffer memory, and a plurality of nonvolatile memory devices, the method including: detecting a power-off event of an external power provided to the storage device; deactivating a host interface of the storage controller in response to the detection of the power-off event: moving data stored in the buffer memory to a static random access memory (SRAM) in the storage controller; blocking or deactivating a power of the buffer memory; setting an interleaving mode of the plurality of nonvolatile memory devices to a minimum power mode; and programming the data moved to the SRAM to at least one of the plurality of nonvolatile memory devices.

A data backup method of a storage device which includes a storage controller, a buffer memory, and a plurality of nonvolatile memory devices, the method including: detecting a power-off event of an external power provided to the storage device; deactivating a host interface of the storage controller in response to the detection of the power-off event: moving data stored in the buffer memory to a static random access memory (SRAM) in the storage controller; blocking or deactivating a power of the buffer memory; setting an interleaving mode of the plurality of nonvolatile memory devices to a minimum power mode; and programming the data moved to the SRAM to at least one of the plurality of nonvolatile memory devices.

In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.

Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.