A semiconductor device which is a processor includes a plurality of first power supply regions in each of which a functional module having a predetermined function is arranged and to which a power supply voltage is individually supplied, a setting unit configured to specify an order of supplying the power supply voltage in the plurality of first power supply regions, and a power controller configured to supply the power supply voltage to the plurality of first power supply regions in accordance with the order specified by the setting unit.

A system is provided that includes a first electronic device, multiple second electronic devices coupled to the first electronic device via respective interfaces, and a clock generator coupled to the second electronic devices and configured to generate and provide a clock signal to each of the second electronic devices for clocking operation of the second electronic devices. The clock signal is a gapped clock signal having at least one gap created by the clock generator removing one or more clock pulses based on a synchronization signal, and the second electronic devices are configured to synchronize data transmission between the second electronic devices and the first electronic device via the interfaces using the at least one gap in the gapped clock signal to align the data transmission.

A system and method of quickly and efficiently generating a series of random numbers from a source of random numbers in a computing system, Steps includes: loading a data loop (a looped array of stored values with an index) with random data from a source of random data; then repeating the following: reading a value from the data loop in relation to the index; operating on the multi-bit value thereby outputting a derived random number; and moving the index in relation to the looped array. The data loop may be a simple feedback loop which may be a shift register loaded by direct memory access (DMA). The operation may be performed by one or more arithmetic logic units (ALU) which may be fed by one or more data feeds and may perform XOR, Mask Generator, Data MUX, and/or MOD.

An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.

A hub may receive event data captured by a body-worn device and store the event data in a memory of the hub. The event data is then backed up from the hub to a memory of an additional hub communicatively connected to the hub. A copy of event data for a predetermined period of time as included in the event data is then transferred from the memory of the hub to a data store of a network operations center (NOC). In response to the transfer being complete, the hub may delete the event data for the predetermined period of time, send a first command to the additional hub directing the additional hub to delete a backup of the event data for the predetermined period of time, or send a second command to the body-worn device directing the body-worn device to delete the event data for the predetermined period of time.

A hub may receive event data captured by a body-worn device and store the event data in a memory of the hub. The event data is then backed up from the hub to a memory of an additional hub communicatively connected to the hub. A copy of event data for a predetermined period of time as included in the event data is then transferred from the memory of the hub to a data store of a network operations center (NOC). In response to the transfer being complete, the hub may delete the event data for the predetermined period of time, send a first command to the additional hub directing the additional hub to delete a backup of the event data for the predetermined period of time, or send a second command to the body-worn device directing the body-worn device to delete the event data for the predetermined period of time.

A system comprises a digital processing circuit, a frequency modulator, an amplitude modulator, and an adder. The digital processing circuit receives an input signal and a correlation signal and generates a frequency tuning parameter and an amplitude modulation parameter. The frequency modulator generates a frequency modulation signal and the correlation signal. The amplitude modulator receives the amplitude modulation parameter and generates an amplitude modulation signal. The adder receives the frequency tuning parameter and the frequency modulation signal and generates a control signal. In some implementations, the system further comprises a DC feedback circuit that receives the input signal and generates a DC compensation signal. In some implementations, the system further comprises a temperature sensor, a temperature compensation circuit, and a second adder.

A system comprises a digital processing circuit, a frequency modulator, an amplitude modulator, and an adder. The digital processing circuit receives an input signal and a correlation signal and generates a frequency tuning parameter and an amplitude modulation parameter. The frequency modulator generates a frequency modulation signal and the correlation signal. The amplitude modulator receives the amplitude modulation parameter and generates an amplitude modulation signal. The adder receives the frequency tuning parameter and the frequency modulation signal and generates a control signal. In some implementations, the system further comprises a DC feedback circuit that receives the input signal and generates a DC compensation signal. In some implementations, the system further comprises a temperature sensor, a temperature compensation circuit, and a second adder.

Disclosed in embodiments of the present disclosure is a system for controlling a laser projector, a laser projector assembly, a terminal, a method for controlling a laser projector, a method for controlling a laser light output, a device for controlling a laser light output and a computer readable storage medium. The system includes a first drive circuit coupled to the laser projector. The first drive circuit is configured to output an electrical signal to drive the laser projector to project laser light and to turn off the laser projector when a duration of outputting the electrical signal is greater than or equal to a preset threshold.

Disclosed in embodiments of the present disclosure is a system for controlling a laser projector, a laser projector assembly, a terminal, a method for controlling a laser projector, a method for controlling a laser light output, a device for controlling a laser light output and a computer readable storage medium. The system includes a first drive circuit coupled to the laser projector. The first drive circuit is configured to output an electrical signal to drive the laser projector to project laser light and to turn off the laser projector when a duration of outputting the electrical signal is greater than or equal to a preset threshold.