G06F1/22

SYSTEMS AND METHODS FOR ELECTRONIC NOTIFICATION QUEUES

A system can include one or more processors and one or more non-transitory computer-readable media storing computing instructions that, when executed on the one or more processors, cause the one or more processors to perform operations: receiving a new notification; determining, using a binary search algorithm, a number of one or more notifications, wherein an interval of the binary search algorithm comprises a time period between a reclamation pointer and an ingestion pointer; when the number of the one or more notifications is greater than a maximum number of notifications, removing, from a central data store, at least one notification of the one or more notifications; and storing the new notification in the central data store. Other embodiments are described.

Low-Power Type-C Receiver with High Idle Noise and DC-Level Rejection

Techniques for low-power USB Type-C receivers with high noise rejection are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to reject the incoming signal even when the incoming signal includes noise with a magnitude of more than 300 mVpp, and to operate in the presence of a VBUS charging current that is compliant with a USB-PD specification.

Low-Power Type-C Receiver with High Idle Noise and DC-Level Rejection

Techniques for low-power USB Type-C receivers with high noise rejection are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to reject the incoming signal even when the incoming signal includes noise with a magnitude of more than 300 mVpp, and to operate in the presence of a VBUS charging current that is compliant with a USB-PD specification.

Pin sharing circuit, pin sharing method, electronic device and electronic wire using the same

Provided herein are a pin sharing circuit, a pin sharing method and an electronic device, an electronic wire using the same. The pin sharing circuit enables at least one pin on an integrated circuit to be shared by a keyboard device and a touch panel and prevents signal interference between the keyboard device and the touch panel using an impedance element disposed on a wire for the pin, such that the pin can output or receive a stimulation signal and a sensor signal that contain both an AC component and a DC component so as to enhance the efficiency of the overall system and prevent the stimulation signal and the sensor signal from conflicts between the keyboard device and the touch panel.

Pin sharing circuit, pin sharing method, electronic device and electronic wire using the same

Provided herein are a pin sharing circuit, a pin sharing method and an electronic device, an electronic wire using the same. The pin sharing circuit enables at least one pin on an integrated circuit to be shared by a keyboard device and a touch panel and prevents signal interference between the keyboard device and the touch panel using an impedance element disposed on a wire for the pin, such that the pin can output or receive a stimulation signal and a sensor signal that contain both an AC component and a DC component so as to enhance the efficiency of the overall system and prevent the stimulation signal and the sensor signal from conflicts between the keyboard device and the touch panel.

No-operation power state command
10209755 · 2019-02-19 · ·

A system comprises a first domain 4 and second domain 6 which communicate via an interface 8. The first domain 4 transmits power state commands to the second domain 6 for controlling transitions of power states at the second domain 6. The power state commands include at least a power up command 50 for triggering a transition to a power up state and a power no-operation command 52 in response to which the second domain remains in the current one of the power states. The no-operation command 52 enables the second domain 6 to be left in either the power up state or a different power state even if the first domain 4 is powered down.

Low-power Type-C receiver with high idle noise and DC-level rejection

Techniques for low-power USB Type-C receivers with high DC-level shift tolerance are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to receive data from an incoming signal on the CC line even when the incoming signal has more than 250 mV of DC offset with respect to local ground, and to operate in presence of a VBUS charging current that is specified in a USB-PD specification.

Low-power Type-C receiver with high idle noise and DC-level rejection

Techniques for low-power USB Type-C receivers with high DC-level shift tolerance are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to receive data from an incoming signal on the CC line even when the incoming signal has more than 250 mV of DC offset with respect to local ground, and to operate in presence of a VBUS charging current that is specified in a USB-PD specification.

COMPONENT COMMUNICATIONS IN SYSTEM-IN-PACKAGE SYSTEMS

A power management device and microprocessor within a System-in-Package (SiP) are provided with communication signals externally available as outputs from the SiP so that they can be configured by an external device. Methods for the configuration of SiPs and Power Management Integrated Circuits (PMICs) packaged within a SiP are also provided.

REVERSIBLE CONNECTOR ORIENTATION DETECTION CIRCUITRY

Reversible connector orientation detection circuitry, reversibly connectible devices having multiple device portions, and methods for determining a connection orientation of multiple device portions of a hardware device are provided herein. A hardware device can include a first device portion and a second device portion. A first resistor can be in a first side of the first device portion. A second resistor can be in a first side of the second device portion, and a third resistor can be in a second side of the second device portion. Connection of the first device portion to the second device portion in different orientations creates, through the resistors, different voltages that can be compared by a digital logic device to indicate orientation. The compared voltages are within either a low voltage range below a digital logic low threshold or a high voltage range above a digital logic high threshold.