According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state of an enable signal, substantially pass the first clock signal to an output signal. The latch circuit may include at least two transistors configured to essentially perform a NAND function and controlled by a second clock signal, wherein the at least two transistors are configured to alter the timing of the substantial passing of the first clock signal to the output signal.

A data fabric routes requests between the plurality of requestors. A probe filter tracks the state of cached lines of memory at a probe filter coupled to the data fabric. Responsive to the data fabric leaving a non-operational power state while all requestors that are probe filter clients are in a non-operational power state, the power management controller delays a probe filter initialization state in which data regarding cached lines is initialized following the non-operational power state.

A method for managing an application and a terminal device. The method includes: launching an application in response to an operation on the application received from a user, wherein a time limit is preset for the application, displaying a notification indicating that a use duration of the application reaches the time limit and a time extension is requested at a predetermined moment before the time limit expires, displaying an interface for an identity authentication after the time extension is selected by the user, and extending the use duration of the application when an identity authentication of the user succeeds. Thus the use duration of the application is manageable and controllable.

A method for managing an application and a terminal device. The method includes: launching an application in response to an operation on the application received from a user, wherein a time limit is preset for the application, displaying a notification indicating that a use duration of the application reaches the time limit and a time extension is requested at a predetermined moment before the time limit expires, displaying an interface for an identity authentication after the time extension is selected by the user, and extending the use duration of the application when an identity authentication of the user succeeds. Thus the use duration of the application is manageable and controllable.

A boot control circuit of a computer system is provided. The boot control circuit is coupled to a system power module. The boot control circuit includes a connection port module and a motherboard. The connection port module includes a detection pin. The motherboard includes a switch for controlling the system power module. The motherboard controls the system power module to provide power for booting the computer system according to a connection between the detection pin and the switch.

Various systems and methods for implementing a soft reset state. A server device includes processing circuitry; and at least one storage device including instructions embodied thereon, wherein the instructions, which when executed by the processing circuitry, configure the processing circuitry to perform operations of a soft reset operation, the operations to: define a soft reset state; cause a check of a secure virtual resource (SVR) of the server device, while in the soft reset state; and transition from the soft reset state in response to an event.

Various systems and methods for implementing a soft reset state. A server device includes processing circuitry; and at least one storage device including instructions embodied thereon, wherein the instructions, which when executed by the processing circuitry, configure the processing circuitry to perform operations of a soft reset operation, the operations to: define a soft reset state; cause a check of a secure virtual resource (SVR) of the server device, while in the soft reset state; and transition from the soft reset state in response to an event.

A power management system includes a first power grid coupled to a first circuit breaker, and a first power distribution unit coupled to the first circuit breaker. A server device includes server components, and at least one first power supply unit coupled to the first power distribution unit. A power management subsystem in the server device is coupled to the server components and the at least one first power supply unit. The power management subsystem monitors a first input current draw of each first power supply unit, and determines whether the first input current draw exceeds a first input current limit that is based on the first circuit breaker. In response the first input current draw exceeding the first input current limit, the power management subsystem throttles the server components to reduce the first input current draw below the first input current limit.

A system and method are provided for controlling a reset procedure. The system has a plurality of power domains, where each power domain comprises a plurality of components, and a plurality of power controllers, wherein each power controller has at last one associated power domain and is arranged to control a supply of power to each associated power domain. The plurality of power controllers are arranged in a hierarchical arrangement comprising two or more hierarchical levels. A given power controller at a given hierarchical level is arranged to implement a reset procedure requiring a reset to be performed in a given reset domain, where the given reset domain comprises at least a subset of the components provided in multiple power domains associated with multiple power controllers provided in at least one hierarchical level below the given hierarchical level. The given power controller is arranged to initiate a reset procedure by issuing a reset entry request for receipt by each of the multiple power controllers. Each power controller is arranged, on accepting the reset entry request, to perform a reset preparation procedure in respect of each associated power domain within the multiple power domains, and then to issue a response signal to confirm that the reset preparation procedure has been performed. In response to detecting that the response signal has been issued by each of the multiple power controllers, the given power controller asserts a reset signal to the multiple power domains providing components of the given reset domain in order to cause the reset to be performed in a synchronised manner in respect of all of the components in the given reset domain.

A system and method are provided for controlling a reset procedure. The system has a plurality of power domains, where each power domain comprises a plurality of components, and a plurality of power controllers, wherein each power controller has at last one associated power domain and is arranged to control a supply of power to each associated power domain. The plurality of power controllers are arranged in a hierarchical arrangement comprising two or more hierarchical levels. A given power controller at a given hierarchical level is arranged to implement a reset procedure requiring a reset to be performed in a given reset domain, where the given reset domain comprises at least a subset of the components provided in multiple power domains associated with multiple power controllers provided in at least one hierarchical level below the given hierarchical level. The given power controller is arranged to initiate a reset procedure by issuing a reset entry request for receipt by each of the multiple power controllers. Each power controller is arranged, on accepting the reset entry request, to perform a reset preparation procedure in respect of each associated power domain within the multiple power domains, and then to issue a response signal to confirm that the reset preparation procedure has been performed. In response to detecting that the response signal has been issued by each of the multiple power controllers, the given power controller asserts a reset signal to the multiple power domains providing components of the given reset domain in order to cause the reset to be performed in a synchronised manner in respect of all of the components in the given reset domain.