Disclosed herein is an information processing apparatus, comprising: a memory configured to store program code; and electric circuitry including a processor, the processor being configured to read and operate according to the program code, the electronic circuitry configured to: set a plurality of candidate values of a parameter tunable in a computer system; trial each of the plurality of set candidate values of the parameter to the computer system for a predetermined period of time or a predetermined number of times and to calculate a reward in the computer system; select, when a trial satisfies a predetermined termination criterion, a candidate value of the parameter for which the maximum reward is calculated among the candidate values of the parameter and apply the selected candidate value of the parameter to the computer system; and re-set candidate values of the parameter based on the selected candidate value of the parameter to repeat.

Disclosed herein is an information processing apparatus, comprising: a memory configured to store program code; and electric circuitry including a processor, the processor being configured to read and operate according to the program code, the electronic circuitry configured to: set a plurality of candidate values of a parameter tunable in a computer system; trial each of the plurality of set candidate values of the parameter to the computer system for a predetermined period of time or a predetermined number of times and to calculate a reward in the computer system; select, when a trial satisfies a predetermined termination criterion, a candidate value of the parameter for which the maximum reward is calculated among the candidate values of the parameter and apply the selected candidate value of the parameter to the computer system; and re-set candidate values of the parameter based on the selected candidate value of the parameter to repeat.

A system and method for logging state data from a power system control device on a computer system is disclosed. The computer system includes a power system supplying power to the computer system. The power system has a power-up sequence having a plurality of stages. The power system control device is coupled to the power system. The power system control device includes a finite state machine circuit having states corresponding to the stages of the power-up sequence. The control device also has a write controller, a storage buffer, and a communication interface. The write controller writes the state of the finite state machine circuit in the storage buffer. An external controller is coupled to the communication interface and is operable to read the stored state data.

Aspects of the invention include computer-implemented methods, systems, and computer program products that assign a centralized event tag to each communication interface of a plurality of communication interfaces of a chip interconnected in a hierarchy through the communication interfaces to a plurality of chips in a multiprocessing system. A determination is performed of whether to accept or drop a message associated with an event received at one of the communication interfaces of the chip based on comparing a local centralized event tag with a received centralized event tag. The local centralized event tag is updated based on one or more advancing rules to maintain event synchronization between the chip and the plurality of chips.

Aspects of the invention include computer-implemented methods, systems, and computer program products that assign a centralized event tag to each communication interface of a plurality of communication interfaces of a chip interconnected in a hierarchy through the communication interfaces to a plurality of chips in a multiprocessing system. A determination is performed of whether to accept or drop a message associated with an event received at one of the communication interfaces of the chip based on comparing a local centralized event tag with a received centralized event tag. The local centralized event tag is updated based on one or more advancing rules to maintain event synchronization between the chip and the plurality of chips.

A processor-enabled method of deleting data of a user on an electronic device of the type having a processor, a volatile memory, a non-volatile memory, a display, and a user interface, includes the steps of A) providing a software application resident in the non-volatile memory of the electronic device, B) running the software application so that the software application is in a standby mode, and c) in an emergency situation, the user using the user interface to activate a data destruction routine of the software application. The data destruction routine performs the steps: 1) turning off the display of the electronic device, or alternately displaying all black pixels on the display, 2) overwriting the data of the user in the non-volatile memory with decoy data, and 3) initiating the factory-reset module. The decoy data may be all zeros, all ones, or random values, for example.

A processor-enabled method of deleting data of a user on an electronic device of the type having a processor, a volatile memory, a non-volatile memory, a display, and a user interface, includes the steps of A) providing a software application resident in the non-volatile memory of the electronic device, B) running the software application so that the software application is in a standby mode, and c) in an emergency situation, the user using the user interface to activate a data destruction routine of the software application. The data destruction routine performs the steps: 1) turning off the display of the electronic device, or alternately displaying all black pixels on the display, 2) overwriting the data of the user in the non-volatile memory with decoy data, and 3) initiating the factory-reset module. The decoy data may be all zeros, all ones, or random values, for example.

An example includes detecting receiving a bus turn-around (BTA) sequence after detecting a voltage level; sending a BTA acknowledgement in response to the BTA sequence; and sending a configuration command to a peripheral device after the interface is initialized based on the BTA acknowledgement.

An example includes detecting receiving a bus turn-around (BTA) sequence after detecting a voltage level; sending a BTA acknowledgement in response to the BTA sequence; and sending a configuration command to a peripheral device after the interface is initialized based on the BTA acknowledgement.

A method and apparatus for starting up a digital currency data processing device, and a digital currency data processing device. The digital currency data processing device includes a hash board including a plurality of hash chip groups. The method includes: transmitting a startup signal to a refrigerating part of a data processing device before turning on a power supply; turning on the power supply; and controlling respective hash chips in each hash chip group to gradually and synchronously turn on cores. The above arrangement improves voltage balance of a hash board, and also ensures the accuracy of a clock signal.