A compute device may include one or more processors operable at variable performance levels depending upon power supplied from a compute device power supply. A baseboard management controller of the compute device may periodically calculate an adjustment value for the power supply to adjust the power delivered to the one or more processors. The adjustment value may be calculated as a function of a thermal margin between the temperature of the one or more processors over time and a thermal operating limit of the one or more processors.

An electronic device capable of placing restrictions on processor usage is disclosed. The electronic device may include: a memory; and a processor including a first core and a second core. The memory may store instructions that, when executed by the processor, cause the first core to transition from an active state to an idle state in response to a restriction signal for the first core, and cause the first core to transition to a power save state when the first core remains in the idle state for at least a preset time. For hot-unplugging, as the electronic device does not transition a core to an offline state, it does not have to perform cleanup operation on the memory and variables. Hence, it is possible to reduce the latency time due to hot-unplugging.

A shared battery system includes a battery having unique identification information, a communication unit communication-connected with a user terminal to receive user information from the user terminal, and an authentication unit configured to perform user authentication based on the user information. A controller is configured to control the authentication unit to perform the user authentication when a communication connection with the user terminal is made, to control the battery to supply electrical energy to a shared mobility device based on a use approval of the shared mobility device when the battery is mounted to the mobility device, to acquire usage information of the shared mobility device therefrom when the electrical energy is supplied to the shared mobility device, and to control the communication unit to transmit the acquired usage information of the shared mobility device and status information of the battery.

A shared battery system includes a battery having unique identification information, a communication unit communication-connected with a user terminal to receive user information from the user terminal, and an authentication unit configured to perform user authentication based on the user information. A controller is configured to control the authentication unit to perform the user authentication when a communication connection with the user terminal is made, to control the battery to supply electrical energy to a shared mobility device based on a use approval of the shared mobility device when the battery is mounted to the mobility device, to acquire usage information of the shared mobility device therefrom when the electrical energy is supplied to the shared mobility device, and to control the communication unit to transmit the acquired usage information of the shared mobility device and status information of the battery.

According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

A method of an electronic device are provided in which current consumption for one or more components of the electronic device is compared with a predetermined current. A first surface temperature of the electronic device is determined based on the comparison and power consumption of the one or more components. A location is detected where heat corresponding to the first surface temperature is generated. A second surface temperature of the electronic device is obtained based on power consumption of a component disposed in the electronic device corresponding to the location where the heat is generated. A target temperature is set based on the obtained second surface temperature. The component is controlled to reduce the power consumption of the component based on the target temperature.

A peak power management (PPM) system is provided for managing peak power operations between two or more NAND memory dies. The PPM system includes a PPM circuit on each NAND memory die. Each PPM circuit includes a first pull-up driver electrically connected to a first power source and a first end of a PPM resistor; a second pull-up driver electrically connected to a second power source and a second end of the PPM resistor; a pull-down driver electrically connected to the second end of the PPM resistor; and a PPM contact pad connected to the second end of the PPM resistor. The PPM contact pads of the two or more NAND memory dies are electrically connected with each other with a common electric potential. The PPM system is configured to manage peak power operations according to the electric potential of the PPM contact pads.

A peak power management (PPM) system is provided for managing peak power operations between two or more NAND memory dies. The PPM system includes a PPM circuit on each NAND memory die. Each PPM circuit includes a first pull-up driver electrically connected to a first power source and a first end of a PPM resistor; a second pull-up driver electrically connected to a second power source and a second end of the PPM resistor; a pull-down driver electrically connected to the second end of the PPM resistor; and a PPM contact pad connected to the second end of the PPM resistor. The PPM contact pads of the two or more NAND memory dies are electrically connected with each other with a common electric potential. The PPM system is configured to manage peak power operations according to the electric potential of the PPM contact pads.

A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.