An analog-digital conversion apparatus may include a control unit configured for receiving an analog-digital (AD) conversion request from a plurality of processing modules; and an analog-digital converter (ADC) configured for performing analog-digital conversion according to the AD conversion request received from the control unit, in which the control unit is configured to integrate the AD conversion request according to periodicity of the AD conversion request and to transfer the integrated AD conversion request to the ADC.

An analog-digital conversion apparatus may include a control unit configured for receiving an analog-digital (AD) conversion request from a plurality of processing modules; and an analog-digital converter (ADC) configured for performing analog-digital conversion according to the AD conversion request received from the control unit, in which the control unit is configured to integrate the AD conversion request according to periodicity of the AD conversion request and to transfer the integrated AD conversion request to the ADC.

A measuring arrangement acquires signals of alternating electrical magnitudes. A sampling apparatus performs a sampling of the signals to form digital sample values. A clock tracking apparatus adapts a sampling clock used by the sampling apparatus in the light of the frequency of the signal to be sampled. In order to be able to acquire reliably signals of alternating electrical magnitudes even when they have different frequencies, the sampling apparatus samples at least two of the signals each with its own sampling clock and the clock tracking apparatus adapts the sampling clock in the light of the frequency of the signal to be sampled simultaneously for each of these at least two signals. There is also described a corresponding method for measuring electrical signals.

A measuring arrangement acquires signals of alternating electrical magnitudes. A sampling apparatus performs a sampling of the signals to form digital sample values. A clock tracking apparatus adapts a sampling clock used by the sampling apparatus in the light of the frequency of the signal to be sampled. In order to be able to acquire reliably signals of alternating electrical magnitudes even when they have different frequencies, the sampling apparatus samples at least two of the signals each with its own sampling clock and the clock tracking apparatus adapts the sampling clock in the light of the frequency of the signal to be sampled simultaneously for each of these at least two signals. There is also described a corresponding method for measuring electrical signals.

Storage administrators would like to create snapshots of a storage array as frequently as possible, but too many concurrent snapshots can place an unnecessary load on the storage array. Described herein are techniques for scheduling snapshots on the storage array with the objective of minimizing the maximum number of simultaneous snapshots and/or temporally spacing apart snapshots from each other.

A system and a method of sampling an event signal using multiple clocking signals each provided in a separate candidate clock domain each of which also receives points in time from a master clock. From each candidate clock domain, clocked by the individual clocking signals, pairs of a received point in time and event signal value are fed to a master clock domain. In the master clock domain, the values of the event signal may be determined over time as a function of master clock time. This may be used for synchronizing operation in the master clock domain of e.g. packet time stamping with an overall time defined by the event signal. Using multiple clocking signals for the sampling, a much more precise sampling of the event signal is facilitated.

A system and a method of sampling an event signal using multiple clocking signals each provided in a separate candidate clock domain each of which also receives points in time from a master clock. From each candidate clock domain, clocked by the individual clocking signals, pairs of a received point in time and event signal value are fed to a master clock domain. In the master clock domain, the values of the event signal may be determined over time as a function of master clock time. This may be used for synchronizing operation in the master clock domain of e.g. packet time stamping with an overall time defined by the event signal. Using multiple clocking signals for the sampling, a much more precise sampling of the event signal is facilitated.

There is disclosed herein integrated circuitry comprising a clock path for carrying a clock signal from a clock source to a circuit block, the circuit block being operable based on the clock signal. Clock buffer circuitry is provided along the clock path for buffering the clock signal. A tuneable inductance is connected to the clock path. A capacitor is connected to the clock path so as to form an AC coupling capacitor connected in series along the path, and is implemented between metal layers of the integrated circuitry.

A display device may include a display panel, a sensor unit, and a touch driver. The sensor unit is provided on the display panel and may output a sensing signal corresponding to a touch input. The sensor unit may include a first electrode and may include a conductive layer provided between the display panel and the first electrode and spaced from the first electrode. The touch driver may include a signal receiver. The signal receiver may include a first input terminal electrically coupled to the first electrode, may include a second input terminal electrically coupled to the conductive layer, may receive the sensing signal, and may output a signal corresponding to a voltage difference the first input terminal and the second input terminal.

A sampling oscilloscope includes a trigger generation circuit that includes a direct digital synthesizer (DDS) that outputs a trigger clock input in an operable frequency range at an arbitrary output frequency, a band pass filter (BPF) that limits a pass band of the trigger clock output from the direct digital synthesizer and a variable frequency divider that divides a frequency of the trigger clock of which the pass band is limited by the band pass filter, and generates a strobe signal of a frequency at which a sampler can be operated. The sampling oscilloscope includes a controller that calculates a phase shift amount with reference to a pattern cycle of data generated by a one-time strobe signal and adjusts a phase by changing a count value of a phase accumulator of the direct digital synthesizer so that the calculated phase shift amount is eliminated.