A test and measurement instrument includes an acquisition memory and a processor structured to store a stream of sampled incoming data samples in the acquisition memory. As the memory fills, the instrument automatically decimates either the data samples already stored in the acquisition memory, the incoming data samples, or both. The instrument may also store two copies of the incoming data samples, one at an increased decimation rate. The two copies are tied together with a timestamp or using other methods. The more highly decimated copy may be used to produce a video output of the stored data samples, saving the instrument from generating the video output from the larger sized sample.

A test and measurement instrument includes an acquisition memory and a processor structured to store a stream of sampled incoming data samples in the acquisition memory. As the memory fills, the instrument automatically decimates either the data samples already stored in the acquisition memory, the incoming data samples, or both. The instrument may also store two copies of the incoming data samples, one at an increased decimation rate. The two copies are tied together with a timestamp or using other methods. The more highly decimated copy may be used to produce a video output of the stored data samples, saving the instrument from generating the video output from the larger sized sample.

An apparatus comprising: circuitry configured to classify a signal; and circuitry configured to control saving of the signal to a memory with a conditional resolution, wherein a signal that is classified as anomalous is saved at higher resolution as a higher resolution signal and a signal that is not classified as anomalous is saved at lower resolution as a lower resolution signal or is not saved.

A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

A data acquisition system comprises a signal processing chain including an analog-to-digital converter (ADC) circuit configured to: produce a digital output from an input signal; detect a specified signal feature of the input signal; and change an operating condition of an additional circuit of the signal processing chain in response to detecting the signal feature of the input signal.

A data acquisition system comprises a signal processing chain including an analog-to-digital converter (ADC) circuit configured to: produce a digital output from an input signal; detect a specified signal feature of the input signal; and change an operating condition of an additional circuit of the signal processing chain in response to detecting the signal feature of the input signal.

In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

To provide a control device and control system capable of implementing time synchronization of sensor data, even in a case of using a common sensor interface device. A control device that receives information related to sensor values from a sensor interface device includes: a timing signal generation unit that generates a timing signal, an additional information generation unit that generates additional information synchronized with the timing signal, and an output unit that outputs the timing signal and additional information to the sensor interface device.