A method includes receiving, by each of an upper shift circuit and a lower shift circuit, an operand for an arithmetic right shift operation. The upper shift circuit is configured to provide an upper output, the lower shift circuit is configured to provide a lower output, and the upper output concatenated with the lower output is a result of the arithmetic right shift operation. The method also includes receiving a shift value for the arithmetic right shift operation; responsive to the shift value, detecting a shift condition in which a portion of, but not all of, the operand could be shifted into bits corresponding to the lower output; and responsive to detecting the shift condition, providing, by a middle shift circuit, at least a portion of the operand to the lower shift circuit as a selectable input.

A method includes receiving, by each of an upper shift circuit and a lower shift circuit, an operand for an arithmetic right shift operation. The upper shift circuit is configured to provide an upper output, the lower shift circuit is configured to provide a lower output, and the upper output concatenated with the lower output is a result of the arithmetic right shift operation. The method also includes receiving a shift value for the arithmetic right shift operation; responsive to the shift value, detecting a shift condition in which a portion of, but not all of, the operand could be shifted into bits corresponding to the lower output; and responsive to detecting the shift condition, providing, by a middle shift circuit, at least a portion of the operand to the lower shift circuit as a selectable input.

Contiguous columns of a convolutional engine are partitioned into two or more groups. Each group of columns may be used to process input data. Filter weights assigned to one group may be distinct from filter weights assigned to another group.

Contiguous columns of a convolutional engine are partitioned into two or more groups. Each group of columns may be used to process input data. Filter weights assigned to one group may be distinct from filter weights assigned to another group.

A processing unit and a method for multiplying at least two multiplicands. The multiplicands are present in an exponential notation, that is, each multiplicand is assigned an exponent and a base. The processing unit is configured to carry out a multiplication of the multiplicands and includes at least one bitshift unit, the bitshift unit shifting a binary number a specified number of places, in particular, to the left; an arithmetic unit, which carries out an addition of two input variables and a subtraction of two input variables; and a storage device. A computer program, which is configured to execute the method, and a machine-readable storage element, in which the computer program is stored, are also described.

A processing unit and a method for multiplying at least two multiplicands. The multiplicands are present in an exponential notation, that is, each multiplicand is assigned an exponent and a base. The processing unit is configured to carry out a multiplication of the multiplicands and includes at least one bitshift unit, the bitshift unit shifting a binary number a specified number of places, in particular, to the left; an arithmetic unit, which carries out an addition of two input variables and a subtraction of two input variables; and a storage device. A computer program, which is configured to execute the method, and a machine-readable storage element, in which the computer program is stored, are also described.

A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multiplied and accumulated. The pairs of floating point values are simultaneously processed by the plurality of MAC processors, each of which output a signed integer form fraction with a first bitwidth and a second bitwith, along with a maximum exponent. The first bitwidth signed integer form fractions are summed by an adder tree using the first bitwidth to form a first sum, and when an excess leading 0 condition is detected, a second adder tree operative on the second bitwidth integer form fractions forms a second sum. The first sum or second sum, along with the maximum exponent, is converted into floating point result.

An electronic device and a controlling method of an electronic device are provided. An electronic device recursively determines a plurality of layers of a neural network model. Weight data of first model information is recursively quantized to obtain a second neural network model. The recursive quantization begins with the weight data and determines an iteration count of a recursion. The recursion operates on error data, quantized weight data, scale data and quantized error data to obtain the iteration count. A first bit-width of the weight data is reduced to a second bit-width of the quantized weight data. The recursion may be performed on a per-layer basis. The weight data may be formulated in a floating-point format and the quantized weight data may be formulated in a fixed point format with an integer number of bits.

Approximation circuitry utilizes bitwise operations on operands to provide approximate results of operations on the operands. A significant digit detector utilizes bitwise operations on the received operands to identify or detect approximate most significant bits in the operands, and then utilizes these identified most significant bits to generate approximate values for each of the operands. Intermediate registers receive and store the approximate values from the significant digit detector. A combinatorial network, such as a lookup table (LUT), thereafter utilizes the approximate values stored in the intermediate registers to generate an approximate result. The approximate result has a value that is an approximate value of a given operation, such as multiplication or division, on the operands provided to the significant digit detector.

Approximation circuitry utilizes bitwise operations on operands to provide approximate results of operations on the operands. A significant digit detector utilizes bitwise operations on the received operands to identify or detect approximate most significant bits in the operands, and then utilizes these identified most significant bits to generate approximate values for each of the operands. Intermediate registers receive and store the approximate values from the significant digit detector. A combinatorial network, such as a lookup table (LUT), thereafter utilizes the approximate values stored in the intermediate registers to generate an approximate result. The approximate result has a value that is an approximate value of a given operation, such as multiplication or division, on the operands provided to the significant digit detector.