G06F5/06

OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS
20170235693 · 2017-08-17 · ·

Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

Data recording and analysis system
11429616 · 2022-08-30 · ·

A system for recording and analyzing a data stream, a method for analyzing a data stream, and a computer readable memory that stores instructions that cause a computer to execute a method of analyzing a data stream are disclosed. The system includes an input port, output port, buffer, and controller. The controller identifies a segment, referred to as a new extracted data segment (EDS) of the data stream stored in a buffer, the new EDS satisfying an extraction protocol. The controller compares the new EDS to each of a plurality of reference data segments (RDSs) using a similarity protocol. A new RDS is created if the new EDS is not similar to an existing EDS. If the new EDS is similar to an RDS, the RDS is updated to list that new EDS as being similar.

Data recording and analysis system
11429616 · 2022-08-30 · ·

A system for recording and analyzing a data stream, a method for analyzing a data stream, and a computer readable memory that stores instructions that cause a computer to execute a method of analyzing a data stream are disclosed. The system includes an input port, output port, buffer, and controller. The controller identifies a segment, referred to as a new extracted data segment (EDS) of the data stream stored in a buffer, the new EDS satisfying an extraction protocol. The controller compares the new EDS to each of a plurality of reference data segments (RDSs) using a similarity protocol. A new RDS is created if the new EDS is not similar to an existing EDS. If the new EDS is similar to an RDS, the RDS is updated to list that new EDS as being similar.

Resetting memory locks in a transactional memory system

A method for resetting of memory locks in a transactional memory system. The method includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The method further includes determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.

Method and system for timeout monitoring

Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.

DATA MANAGEMENT SYSTEM
20170220270 · 2017-08-03 ·

Disclosed herein is a data management system for storing a plurality of incoming data streams. The data management system utilizes a high speed storage device in combination with an intelligent FIFO process to reliably store the incoming data streams to a storage device without fragmentation. The data management system further includes one or more external storage devices that can be used for archival purposes.

Low-skew channel bonding using phase-measuring FIFO buffer
09774478 · 2017-09-26 · ·

Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.

Data Reading Circuit
20170270984 · 2017-09-21 ·

A data reading circuit including a phase difference determining module, a time delay detection module, and a reading control module, and the phase difference determining module is connected to the echo clock signal and a clock signal of the second clock domain. The phase difference determining module is configured to determine a phase difference between the echo clock signal and the clock signal of the second clock domain; the time delay detection module is configured to detect a time delay value in transmission of data from a buffer to a flip-flop; and the reading control module is configured to determine, according to the phase difference and the time delay value, a triggering edge, at which the flip-flop can read data output by the buffer, of the clock signal of the second clock domain.

Data Flow Control For Multi-Chip-Select
20170322767 · 2017-11-09 ·

A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

Operating a FIFO memory

The present invention concerns a method of operating a first-in first-out memory (9) arranged to store measurement data samples measured by a plurality of data measurement sensors (1, 3, 5), which can operate at various sampling rates. The oldest measurement data sample in the memory (9) is arranged to be read first before the newer measurement data samples. The method comprises: receiving measurement data samples from at least two data measurement sensors (1, 3, 5); and saving the received measurement data samples in the memory (9). Each of the measurement data samples saved in the memory is associated with a tag which is also saved in the memory (9) and which identifies the data measurement sensor (1, 3, 5) which measured the respective measurement data sample.