Control apparatus to control operation of a data buffer to which data items are written according to a write pointer which advances in position in response to an input data item rate and from which data items are read according to a read pointer which advances in position in response to an output data item rate, comprises: a detector configured to detect an occupancy difference between a current buffer occupancy and a target buffer occupancy, in which the current buffer occupancy represents a difference between the read and write pointers; an output data item interpolator configured to interpolate a data item at an interpolated data buffer location displaced by a read offset displacement from a data buffer location pointed to by the read pointer; and output control circuitry configured, in response to a current occupancy difference exceeding a threshold occupancy difference, to change the read pointer from an initial read pointer to a target read pointer by a change amount so as to reduce the occupancy difference, the output control circuitry being configured to progressively vary the read offset displacement so as to define an interpolated data buffer location which progresses over the output of a transitional group of data items towards the location pointed to by the target read pointer; the output control circuitry being further configured, when the occupancy difference is less than the threshold occupancy difference and the interpolated data buffer location is aligned with the target read pointer, to inhibit operation of the output data item interpolator and to control output of an output data item from the data buffer location pointed to by the read pointer.

A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

A hardware client and corresponding method employ an object-oriented memory device. The hardware client generates an object-oriented message associated with an object of an object class. The object class includes at least one data member and at least one method. The hardware client transmits the object-oriented message generated to the object-oriented memory device via a hardware communications interface. The hardware communications interface couples the hardware client to the object-oriented memory device. The object is instantiated or to-be instantiated in at least one physical memory of the object-oriented memory device according to the object class. The at least one method enables the object-oriented memory device to access the at least one data member for the hardware client.

Embodiments of the present application provide a communication chip and a data processing method. The communication chip includes a plurality of synchronization modules, a set of buffer modules, and a plurality of alignment modules. The synchronization module is configured to receive data of a corresponding channel, synchronize the received data, and store the synchronized data into the buffer module; the buffer module includes a plurality of first-in-first-out queues FIFO, and the FIFO is configured to buffer the synchronized data output by the corresponding synchronization module; and the alignment module is configured to align the synchronized data of the corresponding channel in the buffer module, and combine and output the aligned data.

Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Switchless interconnect fabric message distribution includes end-to-end partitioning of message pathways or multiple priority levels with interrupt capability. A switchless interconnect fabric message distribution system includes a data distribution module and at least two host-bus adapters connected to the data distribution module. The data distribution module includes partition first in first out buffers. Each of the host-bus adapters includes an input manager connected to input priority first in first out buffers and an output manager connected to priority first in first out buffers.

A circuit includes a buffer, a first programmable real-time unit (PRU), and a second PRU. The first PRU is coupled to the buffer and configured to couple to an input interface. The first PRU is further configured to receive first data sampled by the input interface and receive second data sampled by the input interface. The first PRU is further configured to multiplex the first data and the second data to generate multiplexed data and transmit the multiplexed data to the buffer. The second PRU is coupled to the buffer and configured to couple to an output interface. The second PRU is further configured to obtain the multiplexed data from the buffer and transmit the multiplexed data via an Ethernet physical layer.

Screen response validation of robot execution for robotic process automation (RPA) is disclosed. Whether text, screen changes, images, and/or other expected visual actions occur in an application executing on a computing system that an RPA robot is interacting with may be recognized. Where the robot has been typing may be determined and the physical position on the screen based on the current resolution of where one or more characters, images, windows, etc. appeared may be provided. The physical position of these elements, or the lack thereof, may allow determination of which field(s) the robot is typing in and what the associated application is for the purpose of validation that the application and computing system are responding as intended. When the expected screen changes do not occur, the robot can stop and throw an exception, go back and attempt the intended interaction again, restart the workflow, or take another suitable action.

Screen response validation of robot execution for robotic process automation (RPA) is disclosed. Whether text, screen changes, images, and/or other expected visual actions occur in an application executing on a computing system that an RPA robot is interacting with may be recognized. Where the robot has been typing may be determined and the physical position on the screen based on the current resolution of where one or more characters, images, windows, etc. appeared may be provided. The physical position of these elements, or the lack thereof, may allow determination of which field(s) the robot is typing in and what the associated application is for the purpose of validation that the application and computing system are responding as intended. When the expected screen changes do not occur, the robot can stop and throw an exception, go back and attempt the intended interaction again, restart the workflow, or take another suitable action.

Systems, methods, and apparatus for improving bus latency are described. A data communication method includes receiving a trigger actuation command from a bus master coupled to the serial bus, determining that a sequence is being executed in the slave device, and providing a trigger actuation signal corresponding to the trigger actuation command when execution of the sequence has been completed. A sequence initiation command may be received before the trigger actuation command, and the sequence may be initiated in response to the sequence initiation command. The trigger actuation command may be queued in a first queue, the sequence initiation command in may be queued in a second queue. Trigger actuation commands in the first queue may be associated with sequence initiation commands in the second queue. The sequence may be initiated in response to a sequence initiation command associated with the trigger actuation command corresponding to the trigger actuation signal.