An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.

A data producer stores input data in a buffer in response to a slow clock signal and provides read data from the buffer in response to a read pointer signal. A data movement circuit reads the input data from the buffer using the read pointer signal and provides an update read pointer signal in response to reading the input data. The data movement circuit operates in response to a fast clock signal, and includes a metastable-free synchronizer circuit having inputs for receiving the update read pointer signal, the slow clock signal, and the read pointer signal, and an output for providing a synchronized read pointer signal equal to the read pointer signal except between a change in the read pointer signal while the slow clock signal is active until an inactivation of the slow clock signal. The buffer provides the read data in response to the synchronized read pointer signal.

A method for adjusting audio frequency includes steps of: obtaining initial frequency and temporary data storage of audio data input to a buffering unit; performing a first adjustment procedure on initial frequency to obtain a first variation of temporary data storage corresponding to a first change of initial frequency; calculating a first frequency correction amount according to first variation and a first period of first adjustment procedure; adjusting initial frequency into first frequency according to first frequency correction amount; inputting first frequency into buffering unit; performing a second adjustment procedure on first frequency to obtain a second variation of temporary data storage corresponding to a second change of first frequency; calculating a second frequency correction amount according to second variation and a second period of second adjustment procedure, which first period is less than second period; and adjusting first frequency into target frequency according to second frequency correction amount.

Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow based computations on wavelets of data. Each processing element has a compute element and a routing element. Each compute element has memory. Each router enables communication via wavelets with nearest neighbors in a 2D mesh. A compute element receives a wavelet. If a control specifier of the wavelet is a first value, then instructions are read from the memory of the compute element in accordance with an index specifier of the wavelet. If the control specifier is a second value, then instructions are read from the memory of the compute element in accordance with a virtual channel specifier of the wavelet. Then the compute element initiates execution of the instructions.

Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow based computations on wavelets of data. Each processing element has a compute element and a routing element. Each compute element has memory. Each router enables communication via wavelets with nearest neighbors in a 2D mesh. A compute element receives a wavelet. If a control specifier of the wavelet is a first value, then instructions are read from the memory of the compute element in accordance with an index specifier of the wavelet. If the control specifier is a second value, then instructions are read from the memory of the compute element in accordance with a virtual channel specifier of the wavelet. Then the compute element initiates execution of the instructions.

Provided are a computer program product, system, and method for using at least one machine learning module to select a priority queue from which to process an Input/Output (I/O) request. Input I/O statistics are provided on processing of I/O requests at the queues to at least one machine learning module. Output is received from the at least one machine learning module for each of the queues. The output for each queue indicates a likelihood that selection of an I/O request from the queue will maintain desired response time ratios between the queues. The received output for each of the queues is used to select a queue of the queues. An I/O request from the selected queue is processed.

Provided are a computer program product, system, and method for using at least one machine learning module to select a priority queue from which to process an Input/Output (I/O) request. Input I/O statistics are provided on processing of I/O requests at the queues to at least one machine learning module. Output is received from the at least one machine learning module for each of the queues. The output for each queue indicates a likelihood that selection of an I/O request from the queue will maintain desired response time ratios between the queues. The received output for each of the queues is used to select a queue of the queues. An I/O request from the selected queue is processed.

Methods, systems, apparatus, and circuits for dynamically optimizing the circuit for forward and backward propagation phases of training for neural networks, given a fixed resource budget. The circuits comprising: (1) a specialized circuit that can operate on a plurality of multi-dimensional inputs and weights for the forward propagations phase of neural networks; and (2) a specialized circuit that can operate on either gradients and inputs, or gradients and weights for the backward propagation phase of neural networks. The method comprising: (1) an analysis step to obtain the number of operations and the precision of operations in the forward and backward propagations phases of the neural network; (2) a sampling step to obtain the number of zero-valued activations and gradients during the execution of the neural network; (3) a scheduling and estimation step to obtain the runtime for the forward and backward phases of neural network execution using specialized circuits; (4) a builder step to apply the optimal breakdown of resource budget for the forward and backward phases of the neural network to improve the execution of the Neural Network training for future iterations.

Methods, systems, apparatus, and circuits for dynamically optimizing the circuit for forward and backward propagation phases of training for neural networks, given a fixed resource budget. The circuits comprising: (1) a specialized circuit that can operate on a plurality of multi-dimensional inputs and weights for the forward propagations phase of neural networks; and (2) a specialized circuit that can operate on either gradients and inputs, or gradients and weights for the backward propagation phase of neural networks. The method comprising: (1) an analysis step to obtain the number of operations and the precision of operations in the forward and backward propagations phases of the neural network; (2) a sampling step to obtain the number of zero-valued activations and gradients during the execution of the neural network; (3) a scheduling and estimation step to obtain the runtime for the forward and backward phases of neural network execution using specialized circuits; (4) a builder step to apply the optimal breakdown of resource budget for the forward and backward phases of the neural network to improve the execution of the Neural Network training for future iterations.

A switchable I2S interface including a multiplexer, a switchable FIFO memory and a switchable shift register, is disclosed. The multiplexer receives a transmission instruction or a receiving instruction, and configured to generate a switching signal according to the received instruction. The switchable FIFO memory is connected to the multiplexer and receives the switching signal, and comprise a transmission control circuit and a receiving control circuit. According to the switching signal, the switchable FIFO memory switches on the transmission control circuit to transmit the audio output signal, or switches on the receiving control circuit to receive the audio input signal. The switchable shift register is connected to the switchable FIFO memory, and receives and temporarily stores the audio output signal and the audio input signal.