A method and apparatus for processing numeric calculation are provided. The method includes determining a shift bit and an index bit that falls within an index range of a lookup table from among bits representing a divisor scaled up by an offset, obtaining a replacement value corresponding to an index value of the determined index bit by using the lookup table, multiplying a dividend scaled up by the offset by the obtained replacement value, and outputting a value corresponding to a division operation by correcting a scale of a result of the multiplication using a right shift operation.

A method and apparatus for processing numeric calculation are provided. The method includes determining a shift bit and an index bit that falls within an index range of a lookup table from among bits representing a divisor scaled up by an offset, obtaining a replacement value corresponding to an index value of the determined index bit by using the lookup table, multiplying a dividend scaled up by the offset by the obtained replacement value, and outputting a value corresponding to a division operation by correcting a scale of a result of the multiplication using a right shift operation.

An image processing system includes, a reconfigurable circuit, a storage unit storing first configuration data for a first logical circuit in a predetermined area on the reconfigurable circuit, and second configuration data for a second logical circuit in the predetermined area, and a configuration unit configured to perform first configuration processing for configuring the first logical circuit in the predetermined area, by using the stored first configuration data and predetermined configuration data, on the predetermined area and a different area, and to perform second configuration processing for configuring the second logical circuit in the predetermined area, by using the stored second configuration data and predetermined configuration data, on the predetermined area and the different area. The predetermined configuration data used for the first configuration processing and the predetermined configuration data used for the second configuration processing are not stored in a duplicated way.

According to one embodiment, a calculating device includes a nonlinear oscillator. The nonlinear oscillator includes a circuit part including a first Josephson junction and a second Josephson junction, and a conductive member including a first terminal. An electrical signal is input to the first terminal. The electrical signal includes a first signal in a first operation. The first signal includes a first frequency component having a first frequency, and a second frequency component having a second frequency. The first frequency is 2 times an oscillation frequency of the nonlinear oscillator. An absolute value of a difference between the first frequency and the second frequency is not more than 0.3 times the first frequency.

The present disclosure provides a computation device. The computation device is configured to perform a machine learning computation, and includes an operation unit, a controller unit, and a conversion unit. The storage unit is configured to obtain input data and a computation instruction. The controller unit is configured to extract and parse the computation instruction from the storage unit to obtain one or more operation instructions, and to send the one or more operation instructions and the input data to the operation unit. The operation unit is configured to perform operations on the input data according to one or more operation instructions to obtain a computation result of the computation instruction. In the examples of the present disclosure, the input data involved in machine learning computations is represented by fixed-point data, thereby improving the processing speed and efficiency of training operations.

A reservoir computer. In some embodiments, the reservoir computer includes a Duffing oscillator, and a readout circuit, and the readout circuit is configured to calculate a plurality of products, each of the products being calculated by multiplying a sample, of a plurality of samples of a signal from the Duffing oscillator, by a respective weight of a plurality of weights.

The present disclosure relates to a computing device for processing a multi-bit width value, an integrated circuit board card, a method, and a computer readable storage medium. The computing device may be included in a combined processing apparatus, and the combined processing apparatus may further include a general interconnection interface, and an other processing device. The computing device interacts with the other processing device to jointly complete a computing operation specified by a user. The combined processing apparatus may further include a storage device connected to an apparatus and the other processing device and configured to store data of the apparatus and the other processing device. The solution of the present disclosure can split the multi-bit width value so that the processing capability of the processor is not influenced by the bit width.

A neural network (NN) processing unit includes an operation circuit to perform tensor operations of a given layer of a neural network in one of a first number representation and a second number representation. The NN processing unit further includes a conversion circuit coupled to at least one of an input port and an output port of the operation circuit to convert between the first number representation and the second number representation. The first number representation is one of a fixed-point number representation and a floating-point number representation, and the second number representation is the other one of the fixed-point number representation and the floating-point number representation.

Low precision computers can be efficient at finding possible answers to search problems. However, sometimes the task demands finding better answers than a single low precision search. A computer system augments low precision computing with a small amount of high precision computing, to improve search quality with little additional computing.

Low precision computers can be efficient at finding possible answers to search problems. However, sometimes the task demands finding better answers than a single low precision search. A computer system augments low precision computing with a small amount of high precision computing, to improve search quality with little additional computing.