G06F7/58

Defending neural networks by randomizing model weights

The present disclosure is directed to systems and methods for the selective introduction of low-level pseudo-random noise into at least a portion of the weights used in a neural network model to increase the robustness of the neural network and provide a stochastic transformation defense against perturbation type attacks. Random number generation circuitry provides a plurality of pseudo-random values. Combiner circuitry combines the pseudo-random values with a defined number of least significant bits/digits in at least some of the weights used to provide a neural network model implemented by neural network circuitry. In some instances, selection circuitry selects pseudo-random values for combination with the network weights based on a defined pseudo-random value probability distribution.

Defending neural networks by randomizing model weights

The present disclosure is directed to systems and methods for the selective introduction of low-level pseudo-random noise into at least a portion of the weights used in a neural network model to increase the robustness of the neural network and provide a stochastic transformation defense against perturbation type attacks. Random number generation circuitry provides a plurality of pseudo-random values. Combiner circuitry combines the pseudo-random values with a defined number of least significant bits/digits in at least some of the weights used to provide a neural network model implemented by neural network circuitry. In some instances, selection circuitry selects pseudo-random values for combination with the network weights based on a defined pseudo-random value probability distribution.

STOCHASTIC ROUNDING FOR NEURAL PROCESSOR CIRCUIT
20230236799 · 2023-07-27 ·

Embodiments relate to a neural processor circuit that includes a neural engine and a post-processing circuit. The neural engine performs a computational task related to a neural network to generate a processed value. The post-processing circuit includes a random bit generator, an adder circuit and a rounding circuit. The random bit generator generates a random string of bits. The adder circuit adds the random string of bits to a version of the processed value to generate an added value. The rounding circuit truncates the added value to generate an output value of the computational task. The random bit generator may include a linear-feedback shift register (LFSR) that generates random numbers based on a seed. The seed may be derived from a master seed that is specific to a task of the neural network.

ENHANCEMENTS TO DATAGEN ALGORITHM TO GAIN ADDITIONAL PERFORMANCE
20230236798 · 2023-07-27 ·

One example method includes receiving, from a caller, a call for a data stream of a specified size, initializing the data stream by specifying a first prime number and a second prime number, both of which may be 32-bit primes, and by specifying an available amount of data. The method further includes generating data of the data stream using the first prime number and the second prime number, and transmitting the data of the data stream to the caller until either the data stream has fulfilled the call, or until the available amount of data becomes zero. During the transmitting, the method includes maintaining a running counter that starts at the available amount of data, and decrementing the counter by the amount of data sent to the caller.

Random bit circuit capable of compensating the process gradient
11716842 · 2023-08-01 · ·

A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.

Randomized auction notification
11568488 · 2023-01-31 · ·

A method for performing an auction implemented via an exchange computer system includes receiving, from a user device, a security transaction order, receiving a first matching order, initiating a delay timer that runs for a first period of time, initiating an auction timer that runs for a second period of time, determining that the first period of time has expired, notifying a plurality of market participants of an auction, receiving, during the second period of time, one or more additional matching orders, wherein each of the one or more additional matching orders includes a request for participation in the auction, determining that the second period of time has expired, and facilitating a transaction based on the security transaction order.

Variable input size techniques for neural networks

A neural network, trained on a plurality of random size data samples, can receive a plurality of inference data samples including samples of different sizes. The neural network can generate feature maps of the plurality of inference data samples. Pooling can be utilized to generate feature maps having a fixed size. The fixed size feature maps can be utilized to generate an indication of a class for each of the plurality of inference data samples.

Variable input size techniques for neural networks

A neural network, trained on a plurality of random size data samples, can receive a plurality of inference data samples including samples of different sizes. The neural network can generate feature maps of the plurality of inference data samples. Pooling can be utilized to generate feature maps having a fixed size. The fixed size feature maps can be utilized to generate an indication of a class for each of the plurality of inference data samples.

Constant time updates after memory deduplication
11567684 · 2023-01-31 · ·

Systems and methods are described for resource-efficient memory deduplication and write-protection. In an example, a method includes receiving, by a computing device having a processor, a request to assess deduplication for a plurality of candidate files. The computing device may perform one or more iterative steps for deduplication. The iterative steps may include: receiving, from the plurality of candidate files, a candidate file that is not write-protected; determining, based on a predetermined Bernoulli distribution, a decision to write-protect the candidate file; rendering the candidate file as a write-protected candidate file; determining, based on a review of other candidate files from the plurality of candidate files, that the write-protected candidate file can be deduplicated; and deduplicating the write-protected candidate file.

Method and apparatus for highly effective on-chip quantum random number generator
11567734 · 2023-01-31 · ·

A method for correcting spatially variable electron flux in a true random number generator (TRNG) is presented. The TRNG comprises a radioactive source and an array of detectors, and the method comprises: (a) segmenting the array of detectors into a plurality of groups; (b) for each group: (1) detecting via multiple detectors an electron signal from the decay of the radioactive source; (2) determining a number of detections based on the detection of step (b)(1); (3) determining a group median count based on the number of detections; (4) comparing the group median count to either (A) a detection count from a single detector within the group, or (B) a detection count from multiple detectors within the group; (5) based on the comparison, assigning a value to a string of values; and (c) determining a true random number based on the string of values. A TRNG implementing the method is also disclosed.