A random number generator including: a first ring oscillator including a first inverter chain, the first inverter chain including a plurality of serially connected first inverters, the first ring oscillator configured to output a first random signal generated at a first sub-node between two neighboring first inverters among the plurality of first inverters; a second ring oscillator including a second inverter chain, the second inverter chain including a plurality of serially connected second inverters, the second ring oscillator configured to output a second random signal generated at a second sub-node between two neighboring second inverters among the plurality of second inverters; and a signal processing circuit for generating a random number by combining the first random signal with the second random signal.

Provided are a method and system for using a non-linear feedback shift register (NLFSR) for generating a pseudo-random sequence. The method may include generating, for an n-stage NLFSR that requires more than two taps to generate a maximal length pseudo-random sequence, a pseudo-random sequence using a feedback logical operation of only a first logic gate and a second logic gate. Two non-end taps suitable for providing an at least near-maximal length pseudo-random sequence are inputs for the first logic gate, an output of the first logic gate and an end tap are inputs for the second logic gate, and an output of the second logic gate is used as feedback to a first stage of the n-stage NLFSR.

Technologies are provided for reformulation of a tail query to a head query with the same purchase intent by mapping the tail query to the head query. In some of the technologies, a reasonable embedding can be learned on historical head queries. The embedding can then be refined by leveraging rewards generated from a persistently noisy oracle that compensates for the lack of historical behavioral signal for tail queries. Further, a contextual sampling technique that uses text-based rewards or oracle-based rewards, or both, can be implemented in order to avoid biases introduced by persistent noise in the oracle. Numerical experiments on large scale e-commerce datasets demonstrate that the provided technologies can outperform several conventional approaches to query reformulation.

A random number generator includes a ring oscillator, an inversion selecting circuit, and controller. The ring oscillator includes an inverter chain having at least one inverter and generates an output signal. The inversion selecting circuit controlling a phase inverter configured to invert a signal of the inverter chain. The controller is configured to operate the inversion selecting circuit to provide an output of the first phase inverter to the inverter chain during a first operation mode to measure a frequency of the ring oscillator and operate the inversion selecting circuit to not provide the output of the phase inverter during a second operation mode for generating a random number.

An electronic gaming machine includes a display device, a player input interface configured to receive player input from a player; and a game controller configured to execute instructions. The instructions cause the processor to display a plurality of game reels including a first game reel type having a plurality of symbol positions and a second game reel type including a grouped symbol position. The instructions also cause the processor to display a bonus symbol in the grouped system position and, in response to displaying the bonus symbol, to display an expanded display area comprising at least one additional symbol position located above the reels of the first game reel type. The instructions further cause the processor to determine a game outcome based upon a combination of the at least one additional symbol position and the plurality of symbol positions.

A gaming device having a processor that selects symbols from a first set of reel strips for a plurality of columns of symbol positions, and from a second set of reel strips for a plurality of columns of symbol positions, and controls a display to display the symbols selected including displaying, at each symbol position for which a defined symbol is selected, the defined symbol with the symbol selected at a respective symbol position. Upon the symbols selected including a qualifier symbol, the processor randomly selects one of at least two different symbol replacements, and determines, using the symbol replacements, a replacement symbol for the defined symbol selected. The processor updates the plurality of symbols to incorporate the replacement symbol, and evaluates the updated plurality of symbols for winning symbol combinations.

The invention relates to a method for operating a memory assembly. A physical address is received. The physical address is associated with a first memory segment of a memory assembly. The physical address is modified to a modified physical address. The modified physical address is associated with a second memory segment of the memory assembly.

Devices and techniques for replay protection nonce generation are described herein. A hash, of a first length, can be produced from a first input. A first subset of the hash can be extracted as a selector. A second subset of the hash can be selected using the selector. Here, the second subset has a second length that is less than the first length. The second subset can be transmitted as a nonce for a freshness value in a replay protected communication.

A system and a method for a supply-chain hardware integrity for electronics defense (SHIELD) dielet embedded over a component of a device, a radio frequency identification (RFID) probe system coupled to the SHIELD dielet, and a secure server system communicating with the RFID probe system that can enable security services is provided. Embodiments include a multi-function SHIELD software defined, hardware enabled security system that provides hardware identity, anti-tamper, encryption key generation and management, trusted platform module services, and cryptographic software security services for a device.

An integrated circuit includes signal-source circuitry (SSC), an SSC power supply circuit (SSC-PS) and a digitization circuit. The SSC is configured to generate an output signal, which is guaranteed to meet specified electrical parameters provided that a supply voltage to the SSC is within a specified operating voltage range. The SSC-PS is configured to power the SSC with a reduced voltage that is below the specified operating voltage range, thereby causing the output signal to be noisy. The digitization circuit is configured to digitize the noisy output signal so as to generate a respective sequence of random numbers.